128
References
12. J Appenzeller, Y-M Lin, J Knoch, and Ph Avouris. Band-to-band tunneling in carbon nanotube
field-effect transistors. Physical review letters, 93(19):196805, 2004.
13. Woo Young Choi, Byung-Gook Park, Jong Duk Lee, and Tsu-Jae King Liu. Tunneling fieldeffect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron
Device Letters, 28(8):743–745, 2007.
14. Costin Anghel, Anju Gupta, Amara Amara, Andrei Vladimirescu, et al. 30-nm tunnel FET
with improved performance and reduced ambipolar current. IEEE Transactions on Electron
Devices, 58(6):1649–1654, 2011.
15. A Villalon, C Le Royer, P Nguyen, S Barraud, F Glowacki, A Revelant, L Selmi,
S Cristoloveanu, L Tosti, C Vizioz, et al. First demonstration of strained SiGe nanowires TFETs
with ION beyond 700μA/μm. In VLSI Technology (VLSI-Technology): Digest of Technical
Papers, 2014 Symposium on, pages 1–2. IEEE, 2014.
16. Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee. Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (leq 50mV/decade)
at Room Temperature. IEEE Electron Device Letters, 32(4):437–439, 2011.
17. David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, and Massimo Alioto.
Tunnel FETs for ultralow voltage digital VLSI circuits: Part I Device–circuit interaction and
evaluation at device level. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2488–2498, 2014.
18. R Ranica, N Planes, O Weber, O Thomas, S Haendler, D Noblet, D Croain, C Gardin, and
F Arnaud. FDSOI process/design full solutions for ultra low leakage, high speed and low
voltage SRAMs. In VLSI Technology (VLSIT), 2013 Symposium on, pages T210–T211. IEEE,
2013.
19. Hraziia, Andrei Vladimirescu, Amara Amara, and Costin Anghel. An analysis on the ambipolar
current in Si double-gate tunnel FETs. Solid-State Electronics, 70:67–72, 2012.
20. Adrian M Ionescu and Heike Riel. Tunnel field-effect transistors as energy-efficient electronic
switches. nature, 479(7373):329, 2011.
21. YM Niquet, C Delerue, G Allan, and M Lannoo. Method for tight-binding parametrization:
Application to silicon nanostructures. Physical Review B, 62(8):5109, 2000.
22. Kathy Boucart and Adrian Mihai Ionescu. Double-Gate Tunnel FET With High-K Gate
Dielectric. IEEE Transactions on Electron Devices, 54(7):1725–1733, 2007.
23. C Sandow, J Knoch, C Urban, Q-T Zhao, and S Mantl. Impact of electrostatics and
doping concentration on the performance of silicon tunnel field-effect transistors. Solid-State
Electronics, 53(10):1126–1129, 2009.
24. Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, and Andrei Vladimirescu.
Cmos sensor nodes with sub-picowatt TFET memory. IEEE Sensors Journal, 16(23):8255–
8262, 2016.
25. ASU. Predictive Technology Model, 1999.
26. Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, and Jaydeep P Kulkarni. Variationtolerant ultra low-power heterojunction tunnel FET SRAM design. In Proceedings of the
2011 IEEE/ACM International Symposium on Nanoscale Architectures, pages 45–52. IEEE
Computer Society, 2011.
27. Sneh Saurabh and M Jagadesh Kumar. Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability. IEEE Transactions
on Device and Materials Reliability, 10(3):390–395, 2010.
28. Marcel JM Pelgrom and Aad CJ Duinmaijer. Matching properties of MOS transistors. In
ESSCIRC’88: Fourteenth European Solid-State Circuits Conference, pages 327–330. IEEE,
1988.
29. Saurabh Mookerjea, Ramakrishnan Krishnan, Suman Datta, and Vijaykrishnan Narayanan.
On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device
Letters, 30(10):1102–1104, 2009.
30. Jawar Singh, Krishnan Ramakrishnan, S Mookerjea, Suman Datta, Narayanan Vijaykrishnan,
and D Pradhan. A novel si Tunnel-FET-based SRAM design for ultra low-power 0.3V
VDD applications. In Proceedings of the 2010 Asia and South Pacific Design Automation
Conference, pages 181–186. IEEE Press, 2010.
References
12. J Appenzeller, Y-M Lin, J Knoch, and Ph Avouris. Band-to-band tunneling in carbon nanotube
field-effect transistors. Physical review letters, 93(19):196805, 2004.
13. Woo Young Choi, Byung-Gook Park, Jong Duk Lee, and Tsu-Jae King Liu. Tunneling fieldeffect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron
Device Letters, 28(8):743–745, 2007.
14. Costin Anghel, Anju Gupta, Amara Amara, Andrei Vladimirescu, et al. 30-nm tunnel FET
with improved performance and reduced ambipolar current. IEEE Transactions on Electron
Devices, 58(6):1649–1654, 2011.
15. A Villalon, C Le Royer, P Nguyen, S Barraud, F Glowacki, A Revelant, L Selmi,
S Cristoloveanu, L Tosti, C Vizioz, et al. First demonstration of strained SiGe nanowires TFETs
with ION beyond 700μA/μm. In VLSI Technology (VLSI-Technology): Digest of Technical
Papers, 2014 Symposium on, pages 1–2. IEEE, 2014.
16. Ramanathan Gandhi, Zhixian Chen, Navab Singh, Kaustav Banerjee, and Sungjoo Lee. Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (leq 50mV/decade)
at Room Temperature. IEEE Electron Device Letters, 32(4):437–439, 2011.
17. David Esseni, Manuel Guglielmini, Bernard Kapidani, Tommaso Rollo, and Massimo Alioto.
Tunnel FETs for ultralow voltage digital VLSI circuits: Part I Device–circuit interaction and
evaluation at device level. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2488–2498, 2014.
18. R Ranica, N Planes, O Weber, O Thomas, S Haendler, D Noblet, D Croain, C Gardin, and
F Arnaud. FDSOI process/design full solutions for ultra low leakage, high speed and low
voltage SRAMs. In VLSI Technology (VLSIT), 2013 Symposium on, pages T210–T211. IEEE,
2013.
19. Hraziia, Andrei Vladimirescu, Amara Amara, and Costin Anghel. An analysis on the ambipolar
current in Si double-gate tunnel FETs. Solid-State Electronics, 70:67–72, 2012.
20. Adrian M Ionescu and Heike Riel. Tunnel field-effect transistors as energy-efficient electronic
switches. nature, 479(7373):329, 2011.
21. YM Niquet, C Delerue, G Allan, and M Lannoo. Method for tight-binding parametrization:
Application to silicon nanostructures. Physical Review B, 62(8):5109, 2000.
22. Kathy Boucart and Adrian Mihai Ionescu. Double-Gate Tunnel FET With High-K Gate
Dielectric. IEEE Transactions on Electron Devices, 54(7):1725–1733, 2007.
23. C Sandow, J Knoch, C Urban, Q-T Zhao, and S Mantl. Impact of electrostatics and
doping concentration on the performance of silicon tunnel field-effect transistors. Solid-State
Electronics, 53(10):1126–1129, 2009.
24. Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, and Andrei Vladimirescu.
Cmos sensor nodes with sub-picowatt TFET memory. IEEE Sensors Journal, 16(23):8255–
8262, 2016.
25. ASU. Predictive Technology Model, 1999.
26. Vinay Saripalli, Suman Datta, Vijaykrishnan Narayanan, and Jaydeep P Kulkarni. Variationtolerant ultra low-power heterojunction tunnel FET SRAM design. In Proceedings of the
2011 IEEE/ACM International Symposium on Nanoscale Architectures, pages 45–52. IEEE
Computer Society, 2011.
27. Sneh Saurabh and M Jagadesh Kumar. Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability. IEEE Transactions
on Device and Materials Reliability, 10(3):390–395, 2010.
28. Marcel JM Pelgrom and Aad CJ Duinmaijer. Matching properties of MOS transistors. In
ESSCIRC’88: Fourteenth European Solid-State Circuits Conference, pages 327–330. IEEE,
1988.
29. Saurabh Mookerjea, Ramakrishnan Krishnan, Suman Datta, and Vijaykrishnan Narayanan.
On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device
Letters, 30(10):1102–1104, 2009.
30. Jawar Singh, Krishnan Ramakrishnan, S Mookerjea, Suman Datta, Narayanan Vijaykrishnan,
and D Pradhan. A novel si Tunnel-FET-based SRAM design for ultra low-power 0.3V
VDD applications. In Proceedings of the 2010 Asia and South Pacific Design Automation
Conference, pages 181–186. IEEE Press, 2010.