120
7 Sensing Techniques
Fig. 7.19 Schematic:
adaptive single-ended sense
amplifier
VDD
GND
BLT
VDD
SP1
SAEN & RdnOK
Q1
Q2b
Q2
Q1b
VDD
SP2
BLB
Stronger to shiŌ
imbalance the SA
k
O
d
R
|
b
N
E
A
S
RdOk | SAENb
• In the case of bitline precharged at V DD, the self-adaptive single-ended SA
shown in Fig. 7.19 is used; RdnOk is the inverse of RdOk signal; the SA is
imbalanced in order to perform a single-ended read on BLT while using BLB
precharged at VDD as reference voltage; the SA is imbalanced to favor BLT,
i.e., if BLT does not discharge during read, the SA senses a “1.” Imbalance in
SA can be introduced in various ways; for example, it can be introduced by
sizing asymmetrically the NMOS differential pair in the SA or by changing the
precharge voltage of BLB.
7.5.4 Summary and Applications
The introduced SA architecture for adaptive read is applicable for all the usecases where reliability or voltage scaling is required. Important applications include
embedded systems such as cache memories of processors and memories used in
SoCs designed for the Internet of Things, machine learning, etc. The focus of this
chapter was the design of TFET-CMOS hybrid memories with sensing circuits
implemented in CMOS in order to optimize device dimensions for the same speed as
TFETs, and benefit from accurate transistor variability models available for CMOS
but unavailable for TFETs. As a proof of concept an SRAM macro with adaptive
sensing technique was designed in 28 nm FDSOI CMOS due to limitations imposed
to circuit complexity by present TFET processes. The layout of the 8 Kb test-macro
implemented in a 28 nm FDSOI-CMOS process is shown in Fig. 7.20.
7 Sensing Techniques
Fig. 7.19 Schematic:
adaptive single-ended sense
amplifier
VDD
GND
BLT
VDD
SP1
SAEN & RdnOK
Q1
Q2b
Q2
Q1b
VDD
SP2
BLB
Stronger to shiŌ
imbalance the SA
k
O
d
R
|
b
N
E
A
S
RdOk | SAENb
• In the case of bitline precharged at V DD, the self-adaptive single-ended SA
shown in Fig. 7.19 is used; RdnOk is the inverse of RdOk signal; the SA is
imbalanced in order to perform a single-ended read on BLT while using BLB
precharged at VDD as reference voltage; the SA is imbalanced to favor BLT,
i.e., if BLT does not discharge during read, the SA senses a “1.” Imbalance in
SA can be introduced in various ways; for example, it can be introduced by
sizing asymmetrically the NMOS differential pair in the SA or by changing the
precharge voltage of BLB.
7.5.4 Summary and Applications
The introduced SA architecture for adaptive read is applicable for all the usecases where reliability or voltage scaling is required. Important applications include
embedded systems such as cache memories of processors and memories used in
SoCs designed for the Internet of Things, machine learning, etc. The focus of this
chapter was the design of TFET-CMOS hybrid memories with sensing circuits
implemented in CMOS in order to optimize device dimensions for the same speed as
TFETs, and benefit from accurate transistor variability models available for CMOS
but unavailable for TFETs. As a proof of concept an SRAM macro with adaptive
sensing technique was designed in 28 nm FDSOI CMOS due to limitations imposed
to circuit complexity by present TFET processes. The layout of the 8 Kb test-macro
implemented in a 28 nm FDSOI-CMOS process is shown in Fig. 7.20.