7.5 Adaptive Read Technique
115
VDD
GND
BL
VDD
BLB
SP1
SAENb & RdOkb
Q1
Q2b
Q2
Q1b
VDD
Q1
Q2
Q2b
Q1b
Delayed
Prechg
VDD
GND
RdOK
SAEN | Prech | RdOk
|
N
E
A
S
h
c
e
r
P
|
k
O
d
R
SP2
GND
SP1
SP2
Prech
Precharge circuit
XOR ImplementaƟon
PG1
PG2
a.
b.
c.
Fig. 7.12 Schematic: self-adaptive sense amplifier
SP1 and SP2 charge to an intermediate value with VdiffSP of 0 V. VdiffSP between
SP1 and SP2 starts increasing as the voltage on SP1 starts decreasing once BL starts
discharging; for example, for Vdiff of 100 mV, VdiffSP can be larger than 300 mV
through positive feedback in SA core. Q1 either starts charging back to VDD, if Q1
gets a glitch when Prech is switched OFF, or retains a value near VDD; Q2 starts
discharging to GND. During the start of the operation RdOK is “0.” With Q1 and
Q2 resolving to VDD and GND, respectively, RdOK starts charging to VDD. A
sufficient Vdiff is defined as the differential voltage between BL and BLB, which
generates V diff SP > V off set of the SA. For example, the SA can be designed
with V diff SP ≥ V DD/2, and transistor sizing is done such that Q1 and Q2
are close to GND or VDD for V diff SP ≥ V DD/2. As soon as Q1 and Q2 are
resolved, RdOK goes high notifying that the read operation is finished and the read
value is reliable. A low value on RdOK at the end of the read, i.e., WL low, SAEN
high, and SAENb low, signifies that the read is unreliable and the differential voltage
Vdiff was not sufficient for a proper read operation.
At the level of an n ∗ m memory array the adaptive read technique can be
implemented in different ways; we describe three architectures in the following
subsections.
115
VDD
GND
BL
VDD
BLB
SP1
SAENb & RdOkb
Q1
Q2b
Q2
Q1b
VDD
Q1
Q2
Q2b
Q1b
Delayed
Prechg
VDD
GND
RdOK
SAEN | Prech | RdOk
|
N
E
A
S
h
c
e
r
P
|
k
O
d
R
SP2
GND
SP1
SP2
Prech
Precharge circuit
XOR ImplementaƟon
PG1
PG2
a.
b.
c.
Fig. 7.12 Schematic: self-adaptive sense amplifier
SP1 and SP2 charge to an intermediate value with VdiffSP of 0 V. VdiffSP between
SP1 and SP2 starts increasing as the voltage on SP1 starts decreasing once BL starts
discharging; for example, for Vdiff of 100 mV, VdiffSP can be larger than 300 mV
through positive feedback in SA core. Q1 either starts charging back to VDD, if Q1
gets a glitch when Prech is switched OFF, or retains a value near VDD; Q2 starts
discharging to GND. During the start of the operation RdOK is “0.” With Q1 and
Q2 resolving to VDD and GND, respectively, RdOK starts charging to VDD. A
sufficient Vdiff is defined as the differential voltage between BL and BLB, which
generates V diff SP > V off set of the SA. For example, the SA can be designed
with V diff SP ≥ V DD/2, and transistor sizing is done such that Q1 and Q2
are close to GND or VDD for V diff SP ≥ V DD/2. As soon as Q1 and Q2 are
resolved, RdOK goes high notifying that the read operation is finished and the read
value is reliable. A low value on RdOK at the end of the read, i.e., WL low, SAEN
high, and SAENb low, signifies that the read is unreliable and the differential voltage
Vdiff was not sufficient for a proper read operation.
At the level of an n ∗ m memory array the adaptive read technique can be
implemented in different ways; we describe three architectures in the following
subsections.