116
7 Sensing Techniques
RdOK[0]
RdOK[1]
RdOK[n]
Address Decoder
WL Drivers
Pull-down WL’s@ROK
Bitcell Array
IO-Logic(Sense Amp. + Write logic)
Wired AND
RdOKMEM
Fig. 7.13 Memory architecture with RdOK MEM generation
7.5.2.1 Architecture-1: RdOK to Notify Reliability of Read Operation
In the first proposed architecture the RdOK signals from all the read columns are
wire ANDed and a RdOK MEM signal is generated as shown in Fig. 7.13. This
signal is provided as an output from the memory. This can be utilized by the
system control logic to adapt the system in case of an unreliable read operation.
For example, if RdOK is low at the end of the read operation, the read is repeated
with increased supply voltage. The control can be implemented in hardware or it
can be implemented in software running on the system processor. The RdOK signal
generation from a column correctly read is shown in Fig. 7.14; the waveform for an
unreliable read is shown in Fig. 7.15.
7.5.2.2 Architecture-2: SRAM with Self-Tuning Using RdOK
In this architecture the RdOK signals from all the read columns are used by control
logic inside the memory, see Fig. 7.16. The control logic can adapt the memory in
case of an unreliable read operation; for example, if any of the RdOK’s is low at
the end of the read operation, the read is repeated with increased supply voltage,
lengthened WL pulse-width, or with any kind of read-assist (RA) technique. The
RdOK MEM is also generated to notify the system using the memory that the
last read operation was unreliable and needs to be repeated. This control can be
implemented in BIST, such that during normal operation if any unreliable read is
detected, the memory BIST starts and tunes the memory.
7 Sensing Techniques
RdOK[0]
RdOK[1]
RdOK[n]
Address Decoder
WL Drivers
Pull-down WL’s@ROK
Bitcell Array
IO-Logic(Sense Amp. + Write logic)
Wired AND
RdOKMEM
Fig. 7.13 Memory architecture with RdOK MEM generation
7.5.2.1 Architecture-1: RdOK to Notify Reliability of Read Operation
In the first proposed architecture the RdOK signals from all the read columns are
wire ANDed and a RdOK MEM signal is generated as shown in Fig. 7.13. This
signal is provided as an output from the memory. This can be utilized by the
system control logic to adapt the system in case of an unreliable read operation.
For example, if RdOK is low at the end of the read operation, the read is repeated
with increased supply voltage. The control can be implemented in hardware or it
can be implemented in software running on the system processor. The RdOK signal
generation from a column correctly read is shown in Fig. 7.14; the waveform for an
unreliable read is shown in Fig. 7.15.
7.5.2.2 Architecture-2: SRAM with Self-Tuning Using RdOK
In this architecture the RdOK signals from all the read columns are used by control
logic inside the memory, see Fig. 7.16. The control logic can adapt the memory in
case of an unreliable read operation; for example, if any of the RdOK’s is low at
the end of the read operation, the read is repeated with increased supply voltage,
lengthened WL pulse-width, or with any kind of read-assist (RA) technique. The
RdOK MEM is also generated to notify the system using the memory that the
last read operation was unreliable and needs to be repeated. This control can be
implemented in BIST, such that during normal operation if any unreliable read is
detected, the memory BIST starts and tunes the memory.