114
7 Sensing Techniques
VDD
GND
BL
VDD
BLB
SP1
SAENb
Q1
Q2b
Q2
Q1b
VDD
Q1
Q2
Q2b
Q1b
Delayed
Prechg
VDD
GND
RdOK
SAEN | Prech
|
N
E
A
S
h
c
e
r
P
SP2
GND
SP1
SP2
Prech
Precharge circuit
XOR ImplementaƟon
PG1
PG2
a.
b.
c.
Fig. 7.11 Schematic: proposed sense amplifier
discharging toward zero (depending on whether BL or BLB is discharging), and the
other node tries to remain near VDD. The four output signals of the SA, Q1, Q2,
Q1b, and Q2b are inputs to the XOR gate represented in Fig. 7.11b. A sufficiently
large Vdiff triggers the SA into “1-0” or “0-1” state, which in turn through the
signals applied to the XOR generates the RdOK high only when Q1 and Q2 are
resolved, i.e., the voltage on one is close to VDD and the other close to GND.
If RdOK does not go high before the wordline is deselected, it signifies that the
WL pulse-width is not long enough to read and the read value is not reliable. In
other words, Vdiff between BL and BLB is not sufficient to perform a correct read.
As shown in Fig. 7.12, this scheme can be used in designing adaptive memories to
notify the end of a correct read operation; the RdOK signal can be used to switch
WL OFF and to switch ON the latch behavior of the SA to preserve the read value.
This is achieved by performing the logic functions shown in Fig. 7.12, “SAEN OR
RdOK OR Prech,” and, “SAENb AND RdOKb.” Using this scheme various memory
architectures can be defined either with control logic implemented inside or outside
the memory.
7.5.2 Detailed Description of Functionality
Below is the description of the read operations using the SA shown in Fig. 7.11. At
the start of the read, i.e., selected WL goes high and Prech going low after a delay,
7 Sensing Techniques
VDD
GND
BL
VDD
BLB
SP1
SAENb
Q1
Q2b
Q2
Q1b
VDD
Q1
Q2
Q2b
Q1b
Delayed
Prechg
VDD
GND
RdOK
SAEN | Prech
|
N
E
A
S
h
c
e
r
P
SP2
GND
SP1
SP2
Prech
Precharge circuit
XOR ImplementaƟon
PG1
PG2
a.
b.
c.
Fig. 7.11 Schematic: proposed sense amplifier
discharging toward zero (depending on whether BL or BLB is discharging), and the
other node tries to remain near VDD. The four output signals of the SA, Q1, Q2,
Q1b, and Q2b are inputs to the XOR gate represented in Fig. 7.11b. A sufficiently
large Vdiff triggers the SA into “1-0” or “0-1” state, which in turn through the
signals applied to the XOR generates the RdOK high only when Q1 and Q2 are
resolved, i.e., the voltage on one is close to VDD and the other close to GND.
If RdOK does not go high before the wordline is deselected, it signifies that the
WL pulse-width is not long enough to read and the read value is not reliable. In
other words, Vdiff between BL and BLB is not sufficient to perform a correct read.
As shown in Fig. 7.12, this scheme can be used in designing adaptive memories to
notify the end of a correct read operation; the RdOK signal can be used to switch
WL OFF and to switch ON the latch behavior of the SA to preserve the read value.
This is achieved by performing the logic functions shown in Fig. 7.12, “SAEN OR
RdOK OR Prech,” and, “SAENb AND RdOKb.” Using this scheme various memory
architectures can be defined either with control logic implemented inside or outside
the memory.
7.5.2 Detailed Description of Functionality
Below is the description of the read operations using the SA shown in Fig. 7.11. At
the start of the read, i.e., selected WL goes high and Prech going low after a delay,