List of Figures
xiii
Fig. 6.30 Read waveform for hit and miss conditions [©2016 IEEE] . . . . . . . 102
Fig. 6.31 Write waveform for writing X (10), 0 (00), and 1 (11)
[©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig. 6.32 Memory array organization [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig. 6.33 TCAM dual-bitcell layout [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Fig. 7.1 Imbalanced sense amplifier circuit diagram [©2015 IEEE] . . . . . . . 107
Fig. 7.2 Waveform: Read “0” using imbalanced sense amplifier
[©2015 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Fig. 7.3 Waveform: Read “1” using imbalanced sense amplifier
[©2015 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Fig. 7.4 DPSRAM memory: open-bitlines architecture [©2015
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Fig. 7.5 Circuit diagram—(a) Sense amplifier, (b) Memory output
driver [©2015 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Fig. 7.6 Waveforms for simultaneous read on both ports (see
Fig. 7.4, (a) Port-1 (read “0”), (b) Port-2 (read “1”) [©2015
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Fig. 7.7 Proposed sense amplifier Read circuit [©2016 IEEE] . . . . . . . . . . . . . 111
Fig. 7.8 DC characteristics with different sizing of M 0 with widths
of 200 nm, 400 nm, 600 nm, and 800 nm [©2016 IEEE] . . . . . . . . . . . 111
Fig. 7.9 Different trip points for sensing (5f F load); M 0
sizing—400 nm blue; 600 nm pink; 800 nm orange [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Fig. 7.10 Read delay vs. supply voltage for TFET-CMOS SA with a
5f F load [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Fig. 7.11 Schematic: proposed sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Fig. 7.12 Schematic: self-adaptive sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Fig. 7.13 Memory architecture with RdOK MEM generation . . . . . . . . . . . . . . . . 116
Fig. 7.14 Waveforms: reliable Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Fig. 7.15 Waveforms: unreliable Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Fig. 7.16 Memory architecture with self-tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig. 7.17 Self-adapt memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig. 7.18 Waveforms: adaptive Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Fig. 7.19 Schematic: adaptive single-ended sense amplifier . . . . . . . . . . . . . . . . . . 120
Fig. 7.20 Adaptive memory test-chip photo and layout details . . . . . . . . . . . . . . . 121
xiii
Fig. 6.30 Read waveform for hit and miss conditions [©2016 IEEE] . . . . . . . 102
Fig. 6.31 Write waveform for writing X (10), 0 (00), and 1 (11)
[©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig. 6.32 Memory array organization [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig. 6.33 TCAM dual-bitcell layout [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Fig. 7.1 Imbalanced sense amplifier circuit diagram [©2015 IEEE] . . . . . . . 107
Fig. 7.2 Waveform: Read “0” using imbalanced sense amplifier
[©2015 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Fig. 7.3 Waveform: Read “1” using imbalanced sense amplifier
[©2015 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Fig. 7.4 DPSRAM memory: open-bitlines architecture [©2015
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Fig. 7.5 Circuit diagram—(a) Sense amplifier, (b) Memory output
driver [©2015 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Fig. 7.6 Waveforms for simultaneous read on both ports (see
Fig. 7.4, (a) Port-1 (read “0”), (b) Port-2 (read “1”) [©2015
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Fig. 7.7 Proposed sense amplifier Read circuit [©2016 IEEE] . . . . . . . . . . . . . 111
Fig. 7.8 DC characteristics with different sizing of M 0 with widths
of 200 nm, 400 nm, 600 nm, and 800 nm [©2016 IEEE] . . . . . . . . . . . 111
Fig. 7.9 Different trip points for sensing (5f F load); M 0
sizing—400 nm blue; 600 nm pink; 800 nm orange [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Fig. 7.10 Read delay vs. supply voltage for TFET-CMOS SA with a
5f F load [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Fig. 7.11 Schematic: proposed sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Fig. 7.12 Schematic: self-adaptive sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Fig. 7.13 Memory architecture with RdOK MEM generation . . . . . . . . . . . . . . . . 116
Fig. 7.14 Waveforms: reliable Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Fig. 7.15 Waveforms: unreliable Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Fig. 7.16 Memory architecture with self-tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig. 7.17 Self-adapt memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig. 7.18 Waveforms: adaptive Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Fig. 7.19 Schematic: adaptive single-ended sense amplifier . . . . . . . . . . . . . . . . . . 120
Fig. 7.20 Adaptive memory test-chip photo and layout details . . . . . . . . . . . . . . . 121