xii
List of Figures
Fig. 5.15 Comparison—T CP 2Q for different designs [©2016 IEEE] . . . . . . . . 70
Fig. 5.16 Comparison—T Critical for different designs [©2016 IEEE] . . . . . . . 71
Fig. 6.1 9T-TFET CAM cell [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Fig. 6.2 ReCSAM architecture [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Fig. 6.3 CAM write operation [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Fig. 6.4 CAM search operation, word[0]-CAM hit (BLL0), and
word[1]-worst-case CAM miss (BLL1) [©2016 IEEE] . . . . . . . . . . . . 78
Fig. 6.5 Cell array and dual-bitcell layouts; VDD, BLR, and BLL in
Metal-2; GND, WL1, WL2, and RBL in Metal-3 [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Fig. 6.6 W LP MI N for read/write operations for CAM and SRAM
modes vs. supply voltage [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Fig. 6.7 Memory organization [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Fig. 6.8 Single-ended imbalanced sense amplifier, precharged to “0”
[©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Fig. 6.9 Simulation waveforms of single-ended read during CAM
search [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Fig. 6.10 Chip photo and test-macro layout [©2017 IEEE] . . . . . . . . . . . . . . . . . . 86
Fig. 6.11 Read/write performance [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Fig. 6.12 Read speed with/without SA imbalance tuning [©2017
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Fig. 6.13 VDDmin distribution for ten chips and bitcell leakage. (a)
VDDmin distribution. (b) Bitcell Leakage [©2017 IEEE] . . . . . . . . . 88
Fig. 6.14 Assist techniques analysis, (a) WL boosting, (b) negative
bitline [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Fig. 6.15 Associative memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fig. 6.16 6T-CAM bitcell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fig. 6.17 Winner-take-all implementation for two columns . . . . . . . . . . . . . . . . . . 92
Fig. 6.18 Winner-take-all logic for one memory bank; one WTA per
column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Fig. 6.19 Search operation waveform, simulation condition
(mismatch): Col[0]-4 bit, Col[1]-3 bit, Col[2]-1 bit . . . . . . . . . . . . . . . . 94
Fig. 6.20 Write operation with bitcell ground at V DD/2 . . . . . . . . . . . . . . . . . . . . 95
Fig. 6.21 TFET associative memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Fig. 6.22 8T-TFET associative memory compatible bitcell . . . . . . . . . . . . . . . . . . 96
Fig. 6.23 10T-CMOS CAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Fig. 6.24 Bitcell array of 10T-NOR CAM-based associative memory . . . . . . . 98
Fig. 6.25 Overall memory organization with WTA logic on match lines . . . . 98
Fig. 6.26 Current-mode WTA circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Fig. 6.27 Current-mode WTA-based comparison logic for associative
memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Fig. 6.28 Associative memory test-chip photo and block layout
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Fig. 6.29 Hybrid TFET/CMOS 7T-TCAM bitcell [©2016 IEEE] . . . . . . . . . . . 101
List of Figures
Fig. 5.15 Comparison—T CP 2Q for different designs [©2016 IEEE] . . . . . . . . 70
Fig. 5.16 Comparison—T Critical for different designs [©2016 IEEE] . . . . . . . 71
Fig. 6.1 9T-TFET CAM cell [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Fig. 6.2 ReCSAM architecture [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Fig. 6.3 CAM write operation [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Fig. 6.4 CAM search operation, word[0]-CAM hit (BLL0), and
word[1]-worst-case CAM miss (BLL1) [©2016 IEEE] . . . . . . . . . . . . 78
Fig. 6.5 Cell array and dual-bitcell layouts; VDD, BLR, and BLL in
Metal-2; GND, WL1, WL2, and RBL in Metal-3 [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Fig. 6.6 W LP MI N for read/write operations for CAM and SRAM
modes vs. supply voltage [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Fig. 6.7 Memory organization [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Fig. 6.8 Single-ended imbalanced sense amplifier, precharged to “0”
[©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Fig. 6.9 Simulation waveforms of single-ended read during CAM
search [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Fig. 6.10 Chip photo and test-macro layout [©2017 IEEE] . . . . . . . . . . . . . . . . . . 86
Fig. 6.11 Read/write performance [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Fig. 6.12 Read speed with/without SA imbalance tuning [©2017
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Fig. 6.13 VDDmin distribution for ten chips and bitcell leakage. (a)
VDDmin distribution. (b) Bitcell Leakage [©2017 IEEE] . . . . . . . . . 88
Fig. 6.14 Assist techniques analysis, (a) WL boosting, (b) negative
bitline [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Fig. 6.15 Associative memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fig. 6.16 6T-CAM bitcell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fig. 6.17 Winner-take-all implementation for two columns . . . . . . . . . . . . . . . . . . 92
Fig. 6.18 Winner-take-all logic for one memory bank; one WTA per
column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Fig. 6.19 Search operation waveform, simulation condition
(mismatch): Col[0]-4 bit, Col[1]-3 bit, Col[2]-1 bit . . . . . . . . . . . . . . . . 94
Fig. 6.20 Write operation with bitcell ground at V DD/2 . . . . . . . . . . . . . . . . . . . . 95
Fig. 6.21 TFET associative memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Fig. 6.22 8T-TFET associative memory compatible bitcell . . . . . . . . . . . . . . . . . . 96
Fig. 6.23 10T-CMOS CAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Fig. 6.24 Bitcell array of 10T-NOR CAM-based associative memory . . . . . . . 98
Fig. 6.25 Overall memory organization with WTA logic on match lines . . . . 98
Fig. 6.26 Current-mode WTA circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Fig. 6.27 Current-mode WTA-based comparison logic for associative
memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Fig. 6.28 Associative memory test-chip photo and block layout
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Fig. 6.29 Hybrid TFET/CMOS 7T-TCAM bitcell [©2016 IEEE] . . . . . . . . . . . 101