List of Figures
xi
Fig. 4.2 TFET I D = f (reverse-biased V DS ) characteristics and
capacitor leakage [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Fig. 4.3 Signals during write [©2017 IEEE] ................................. 48
Fig. 4.4 Write waveforms [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Fig. 4.5 Signals during read, (a) selected cell and (b)
partially-selected cells due to precharged BLs [©2017 IEEE] . . . . . 50
Fig. 4.6 Read waveforms [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig. 4.7 2 × 2 Bitcell array organization [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . 51
Fig. 4.8 uDRAM bitcell layout [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Fig. 4.9 2T1C uSRAM bitcell (retention bias voltages) [©2017
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Fig. 4.10 Read waveforms showing two RBLs (read “0” and read “1”)
with active low WL. Internal cell nodes retain data during
read [©2017 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Fig. 4.11 2T1C uSRAM bitcell array organization [©2017 IEEE] . . . . . . . . . . . 53
Fig. 4.12 uSRAM bitcell layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Fig. 4.13 3T1C uCAM bitcell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Fig. 4.14 uCAM read: hit and miss conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Fig. 4.15 uCAM 2x2 bitcell array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Fig. 4.16 uCAM bitcell layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Fig. 5.1 TFET transmission-gate flip-flop [©2013 IEEE] . . . . . . . . . . . . . . . . . . . 60
Fig. 5.2 TFET master-slave flip-flop [©2013 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . 61
Fig. 5.3 TFET semi-dynamic flip-flop [©2013 IEEE] . . . . . . . . . . . . . . . . . . . . . . . 61
Fig. 5.4 TFET sense amplifier-based latch [©2013 IEEE] . . . . . . . . . . . . . . . . . . 62
Fig. 5.5 TFET sense amplifier-based flip-flop [©2013 IEEE] . . . . . . . . . . . . . . 62
Fig. 5.6 TFET pseudo-static flip-flop [©2013 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . 63
Fig. 5.7 Proposed 12T (14T with O/P driver-2) TFET-FF design
[©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Fig. 5.8 Flip-flop voltage waveforms, (a) Input data and clock, (b)
inverted output, and (c) FF internal nodes . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Fig. 5.9 12T-TFET FF comparison with LP-CMOS and FinFET
FF’s: leakage power vs. supply voltage [©2016 IEEE] . . . . . . . . . . . . 66
Fig. 5.10 12T-TFET FF comparison with LP-CMOS and FinFET
FF’s: dynamic power consumption vs. supply voltage
[©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Fig. 5.11 12T-TFET FF comparison with LP-CMOS and FinFET
FF’s: T Setup vs. supply voltage [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . 67
Fig. 5.12 12T-TFET FF comparison with LP-CMOS and FinFET
FF’s: T CP 2Q vs. supply voltage [©2016 IEEE] . . . . . . . . . . . . . . . . . . . . 67
Fig. 5.13 12T-TFET FF comparison with LP-CMOS and FinFET
FF’s: maximum operating frequency vs. supply voltage
[©2016 IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Fig. 5.14 Comparison—T Setup for different flip-flop designs [©2016
IEEE] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69