7.3 Charge-Injection-Based Single-Ended Imbalanced Sense Amplifier with. . .
109
BL Drivers
SA[62]
(BLR1 SA)
Col[0]-64x1
Col[7]-64x1
SA[63]
(BLR2 SA)
Col[7]-64x1
Col[0]-64x1
2-Muxes-8x1
Muxes-8x1
WL Drivers
Row Dec.
SA[0-63]
BL Drivers
TFET
SRAM
Array
64x256
Write Logic
BL Drivers
TFET
SRAM
Array
64x256
Write Logic
Muxes-8x1
WL Drivers
Row Dec.
Column Dec.
Muxes-8x1
SA[0-63]
BL Drivers
TFET
SRAM
Array
64x256
Write Logic
TFET
SRAM
Array
64x256
Write Logic
Muxes-8x1
BLR1_Top[248]
BLR2_Top[248]
2-Muxes-8x1
BLR1_Top[255]
BLR2_Top[255]
BLR1_Bot[248]
BLR2_Bot[248]
BLR1_Bot[255]
BLR2_Bot[255]
BLR1_Top
BLR2_Top
BLR1_Bot
BLR2_Bot
Fig. 7.4 DPSRAM memory: open-bitlines architecture [©2015 IEEE]
1
p
a
C
S
O
M
VDD
En_Bot
En_Top
SAEN
p
o
T
_
R
L
B
BLR_Bot
SAEN
SAEN
MOSCap2
Qb
Q
EN_Top
EN_Bot
VDD
GND
Q
Qb
EN_Bot
EN_Top
VDD
GND
Part-I
Part-II
QP1
QP2
RdOut
Q
Qb
a.
b.
Fig. 7.5 Circuit diagram—(a) Sense amplifier, (b) Memory output driver [©2015 IEEE]
goes high with SAEN while En_Bot remains low. Signal QP1 in Part-I of the circuit
shown in Fig. 7.5b drives the output RdOut while node QP2 in Part-II of the circuit
is in tri-state. Similarly, for reading a cell on BLR_Bot, En_Top is low, En_Bot goes
high with SAEN, QP1 is in tri-state and QP2 drives the output RdOut. Depending