7.2 Charge-Injection-Based Single-Ended Imbalanced SenseAmplifier
107
Fig. 7.1 Imbalanced sense
amplifier circuit diagram
[©2015 IEEE]
MOSCap1
MOSCap2
VDD
VDD
SAEN
BLR
VDD
SAEN
SAEN
Q
Qb
SAEN
Fig. 7.2 Waveform: Read
“0” using imbalanced sense
amplifier [©2015 IEEE]
0
0.2
0.4
0.6
0.8
1
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V(SA.Q)
V(SA.QB)
Time (ns)
Voltage (V)
Voltage (V)
0.64
0.84
1.04
0.53
0.57
0.0
0.5
1.0
V(SAEN)
V(WL1)
V(BLR1)
see Fig. 7.1. In the case of reading a “0,” the bitline discharge should be more than
100 mV in order to be read correctly. For the case of reading a “1” BLR remains
at the precharged value (VDD) and the SA will resolve with node Q kept at “1.” In
order to ensure correct functionality taking into account parameter variations, the
SA is designed with a 3-sigma offset of 50 mV. Therefore, to ensure correct read
operation BLR should discharge by 150 mV for reading a “0.” For reading a “1,”
BLR should discharge less than 50 mV including noise, leakage, and variations. As
shown in Fig. 7.1, the imbalance is designed with charge injection using MOSFET
capacitors. MOSCap1 is sized to inject a charge generating a 100 mV impulse on
SA internal node Q. To balance the capacitance on both nodes of the SA in order
to minimize offset, an identical-valued capacitor MOSCap2 is placed on Qb but
connected to VDD such that it does not inject charge into node Qb. Figures 7.2
and 7.3 show read waveforms for “0” and “1,” respectively; V(WL1) is the word
selection signal applied to the cells in the first-row of the memory array.
107
Fig. 7.1 Imbalanced sense
amplifier circuit diagram
[©2015 IEEE]
MOSCap1
MOSCap2
VDD
VDD
SAEN
BLR
VDD
SAEN
SAEN
Q
Qb
SAEN
Fig. 7.2 Waveform: Read
“0” using imbalanced sense
amplifier [©2015 IEEE]
0
0.2
0.4
0.6
0.8
1
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V(SA.Q)
V(SA.QB)
Time (ns)
Voltage (V)
Voltage (V)
0.64
0.84
1.04
0.53
0.57
0.0
0.5
1.0
V(SAEN)
V(WL1)
V(BLR1)
see Fig. 7.1. In the case of reading a “0,” the bitline discharge should be more than
100 mV in order to be read correctly. For the case of reading a “1” BLR remains
at the precharged value (VDD) and the SA will resolve with node Q kept at “1.” In
order to ensure correct functionality taking into account parameter variations, the
SA is designed with a 3-sigma offset of 50 mV. Therefore, to ensure correct read
operation BLR should discharge by 150 mV for reading a “0.” For reading a “1,”
BLR should discharge less than 50 mV including noise, leakage, and variations. As
shown in Fig. 7.1, the imbalance is designed with charge injection using MOSFET
capacitors. MOSCap1 is sized to inject a charge generating a 100 mV impulse on
SA internal node Q. To balance the capacitance on both nodes of the SA in order
to minimize offset, an identical-valued capacitor MOSCap2 is placed on Qb but
connected to VDD such that it does not inject charge into node Qb. Figures 7.2
and 7.3 show read waveforms for “0” and “1,” respectively; V(WL1) is the word
selection signal applied to the cells in the first-row of the memory array.