106
7 Sensing Techniques
analysis of performance, area, and power constraints; various architectures were
proposed, including new kind of memory cells, flexible ECC implementations,
and run-time configurable-memory architectures [91–94]. The most interesting
proposals are reviewed below.
The design presented in [91] uses cells of different sizes in the same memory
in order to optimize area vs. error rate. MSBs are stored in larger cells and LSBs
are stored in smaller cells. In [92], the authors proposed a flexible architecture
where write assist (WA) and ECC can be enabled partially whenever needed. The
number of ECC bits can also be increased to afford more soft errors in MSBs
with the ECC bits stored in LSBs. In [93], an adaptive memory architecture is
presented using dual imbalanced sense amplifiers in place of a single balanced
SA. In [94], an adaptive write wordline (WWL) pulse-width modulation scheme
is described. Write completion is monitored every cycle; when write completion
is detected, a Built-In-Self-Test (BIST) stops the write operation; with this, the
presented architecture supports adaptive WWL voltage-level modulation to work as
WA. The WWL is boosted after the first cycle in order to assist the write operation
while half-selected bitcells are not disturbed due to bitline regeneration during the
cycle. Since the majority of the memory area, especially for SRAMs, is occupied by
bitcells, it is important to minimize bitcell area. Therefore, for adaptive memories
it is important that the sense and write circuits implement this feature without
impacting conventional bitcell design and sizing.
The first part of this chapter focuses on different single-ended techniques useful
for TFET and/or CMOS memories. In the latter part adaptive sensing techniques
and their application in memory architectures are presented. The sensing techniques
presented in this chapter are introduced for use in TFET-CMOS hybrid memories.
However, these techniques are equally useful in TFET-only memories, and most
of them, which are not using any TFET-specific properties are also applicable for
CMOS-only memories.
7.2 Charge-Injection-Based Single-Ended Imbalanced Sense
Amplifier
This section presents single-ended sensing using an imbalanced differential SA
based on charge injection described in [50]. An imbalanced SA is shown in Fig. 7.1.
It can be noticed that one input serves as reference connected at VDD and the other
input, the sensing node, is connected at the bitline to be read, BLR. Therefore, with
a balanced single-ended SA it is not possible to read a “1” using VDD precharged
bitlines as in the case of a differential SA because BLR is at VDD and the other
SA node, its reference, is also precharged at VDD. The design principle of an
imbalanced SA uses charge injection to create an imbalance for removing the
reference voltage source and uses symmetric sizing of devices in order to minimize
variations. The read scheme uses an SA imbalanced by 100 mV relative to BLR,
7 Sensing Techniques
analysis of performance, area, and power constraints; various architectures were
proposed, including new kind of memory cells, flexible ECC implementations,
and run-time configurable-memory architectures [91–94]. The most interesting
proposals are reviewed below.
The design presented in [91] uses cells of different sizes in the same memory
in order to optimize area vs. error rate. MSBs are stored in larger cells and LSBs
are stored in smaller cells. In [92], the authors proposed a flexible architecture
where write assist (WA) and ECC can be enabled partially whenever needed. The
number of ECC bits can also be increased to afford more soft errors in MSBs
with the ECC bits stored in LSBs. In [93], an adaptive memory architecture is
presented using dual imbalanced sense amplifiers in place of a single balanced
SA. In [94], an adaptive write wordline (WWL) pulse-width modulation scheme
is described. Write completion is monitored every cycle; when write completion
is detected, a Built-In-Self-Test (BIST) stops the write operation; with this, the
presented architecture supports adaptive WWL voltage-level modulation to work as
WA. The WWL is boosted after the first cycle in order to assist the write operation
while half-selected bitcells are not disturbed due to bitline regeneration during the
cycle. Since the majority of the memory area, especially for SRAMs, is occupied by
bitcells, it is important to minimize bitcell area. Therefore, for adaptive memories
it is important that the sense and write circuits implement this feature without
impacting conventional bitcell design and sizing.
The first part of this chapter focuses on different single-ended techniques useful
for TFET and/or CMOS memories. In the latter part adaptive sensing techniques
and their application in memory architectures are presented. The sensing techniques
presented in this chapter are introduced for use in TFET-CMOS hybrid memories.
However, these techniques are equally useful in TFET-only memories, and most
of them, which are not using any TFET-specific properties are also applicable for
CMOS-only memories.
7.2 Charge-Injection-Based Single-Ended Imbalanced Sense
Amplifier
This section presents single-ended sensing using an imbalanced differential SA
based on charge injection described in [50]. An imbalanced SA is shown in Fig. 7.1.
It can be noticed that one input serves as reference connected at VDD and the other
input, the sensing node, is connected at the bitline to be read, BLR. Therefore, with
a balanced single-ended SA it is not possible to read a “1” using VDD precharged
bitlines as in the case of a differential SA because BLR is at VDD and the other
SA node, its reference, is also precharged at VDD. The design principle of an
imbalanced SA uses charge injection to create an imbalance for removing the
reference voltage source and uses symmetric sizing of devices in order to minimize
variations. The read scheme uses an SA imbalanced by 100 mV relative to BLR,