Chapter 7
Sensing Techniques
7.1 Introduction
Conventional differential sensing is used in most CMOS memories; single-ended
sensing has already been reported in literature and used in CMOS memories but
is limited to specific use-cases such as 8T-CMOS SRAM, CMOS-DRAM, Flash,
non-volatile memories [51–53]. Single-ended sensing is a promising option to
use for optimized TFET memory cells due to the unidirectionality property of
TFETs, which represents an obstacle for providing a differential output to the SA.
Therefore, most state-of-the-art TFET memories are using single-ended sensing
for read. Most TFET memory bitcells presented in literature have static power
consumption several decades below that of their CMOS counterparts but exhibit
limited performance. Therefore, the main challenge for designing single-ended
sensing for TFET memories is to reliably differentiate “1” and “0” while limiting
the required bitline voltage drop with a compact Sense Amplifier (SA), as for many
applications the SA has to fit in the column pitch. Especially for compact memories,
such as the 3T-TFET bitcell memory presented in Chap. 3, either a standard SA with
tall and inefficient layout or an inverter-based SA can be used to meet the column
pitch.
In the case of single-ended sensing using a differential SA a voltage source is
needed to generate the reference voltage while for inverter-based sensing the bitline
needs to be discharged below the trip point of the inverter, which often results in a
full discharge, leading to a slow operation and higher dynamic power consumption
for read. To alleviate these problems and improve speed an inverter-based sense
keeper can be implemented in the read circuit [52].
Another aspect capturing the attention of researchers are adaptive memory
techniques. Adaptive techniques are useful in various ways for increasing the
reliability at low voltages and minimizing design time margins leading to speed and
power improvement. These techniques are reported in literature in SRAM designs
adaptive in terms of architecture. A lot of research is done on memories toward the
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_7
105
Sensing Techniques
7.1 Introduction
Conventional differential sensing is used in most CMOS memories; single-ended
sensing has already been reported in literature and used in CMOS memories but
is limited to specific use-cases such as 8T-CMOS SRAM, CMOS-DRAM, Flash,
non-volatile memories [51–53]. Single-ended sensing is a promising option to
use for optimized TFET memory cells due to the unidirectionality property of
TFETs, which represents an obstacle for providing a differential output to the SA.
Therefore, most state-of-the-art TFET memories are using single-ended sensing
for read. Most TFET memory bitcells presented in literature have static power
consumption several decades below that of their CMOS counterparts but exhibit
limited performance. Therefore, the main challenge for designing single-ended
sensing for TFET memories is to reliably differentiate “1” and “0” while limiting
the required bitline voltage drop with a compact Sense Amplifier (SA), as for many
applications the SA has to fit in the column pitch. Especially for compact memories,
such as the 3T-TFET bitcell memory presented in Chap. 3, either a standard SA with
tall and inefficient layout or an inverter-based SA can be used to meet the column
pitch.
In the case of single-ended sensing using a differential SA a voltage source is
needed to generate the reference voltage while for inverter-based sensing the bitline
needs to be discharged below the trip point of the inverter, which often results in a
full discharge, leading to a slow operation and higher dynamic power consumption
for read. To alleviate these problems and improve speed an inverter-based sense
keeper can be implemented in the read circuit [52].
Another aspect capturing the attention of researchers are adaptive memory
techniques. Adaptive techniques are useful in various ways for increasing the
reliability at low voltages and minimizing design time margins leading to speed and
power improvement. These techniques are reported in literature in SRAM designs
adaptive in terms of architecture. A lot of research is done on memories toward the
© Springer Nature Switzerland AG 2021
N. Gupta et al., TFET Integrated Circuits,
https://doi.org/10.1007/978-3-030-55119-3_7
105