6.4 Associative Memory Architecture
99
GND
vc
VDD
I 1
VDD
GND
VDD
I 2
VDD
GND
VDD
I N
VDD
I c
GND
vout 1
vout 2
vout N
Fig. 6.26 Current-mode WTA circuit
bit
bit_b
word
match
cell
cell_b
ML
Memcell
Memcell
Memcell
ML
word
WTA
PRE_WTA_N
GND
Current Mirror
vc
vout
vc
VDD
PRE_WTA_N
VDD
PRE_WTA_N
I Read
I Read
WTA
Fig. 6.27 Current-mode WTA-based comparison logic for associative memories