98
6 Content-Addressable Memories
Fig. 6.23 10T-CMOS CAM
cell
bit
bit_b
word
match
cell
cell_b
ML [0]
ML [1]
ML [N]
WORD
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
Memcell
WTA
Winner -Take-All Logic
SA
Write word line
drivers
WTA
WTA
SA
SA
bit
bit_b
bit_b
bit_b
bit
bit
Fig. 6.24 Bitcell array of 10T-NOR CAM-based associative memory
BL Drivers
WL Drivers + WL logic
Data In
(write data or search data)
RowDec
Address In
N-bit output (only cold or one
hot encoded)
SA
Match0
SA
Match
SA
Match
Comparison Logic (WTA)
Bitcell Array
(10T-NOR CAM)
WL[0]
WL[1]
WL[N]
ML[0]
ML[1]
ML[N]
Fig. 6.25 Overall memory organization with WTA logic on match lines