6.4 Associative Memory Architecture
97
in a single column to perform two parallel search operations and one- or twoword write at any given time. BLRs are used as match lines with active pull-ups.
WTA comparison logic is used to compare all match lines in order to find the
closest match. Comparison provides one-cold encoded output, which is followed
by sense amplifiers to fully resolve the matching and provide digital outputs. The
same WTA comparison logic shown in Fig. 6.17 can be used for TFET memories
as well. In order to achieve the maximum discharge current on BLR for the closest
match, Fig. 6.21, it is necessary to get the maximum number of zeroes connected
to BLR during a match, see the detailed explanation in Sect. 6.4.1 above. In case of
mismatch, the bitcell node storing a “1” is connected to bitline BLR, therefore, there
is no BLR discharge through mismatched bits. In case of a match BLR is discharged
either through node V1 or node V2 depending on the selected wordline. In case
of a partial match BLR discharges through a single or multiple bitcells depending
on the number of matching bits. In order to find the closest match, the maximum
BLR discharge current through bitcells with bitline pull-up switched ON needs to
be detected. The BLR voltage will be decided by the ratio of the resistance of BLR
pull-up and BLR discharge path through bitcells for matched bits. BLR1 and BLR2
are used to search simultaneously for two words, one from the upper half of the
column and the other from the lower half (see Fig. 6.21), respectively. The two BLRs
work identically as described above, each with its own WTA logic block.
The write operation is performed in a similar way to the SRAM, except that
the BLW for the selected word, i.e. one column, is activated by pulling it low and
selecting WL’s according to the data. Two-word write is possible by activating WL’s
for both sets of words and pulling BLW low.
6.4.2.2 Associative Memory Using Standard 10T-NOR CAM Bitcell
The proposed associative memory can also be implemented in CMOS using a
standard 10T-NOR CAM bitcell shown in Fig. 6.23. Similar comparison logic as
the one shown in Fig. 6.17, is implemented on match lines with match precharge
ON during search operation. The basic architecture is shown in Fig. 6.24 and overall
memory organization is shown in Fig. 6.25. Write is performed using bit and bit_b
lines as data lines with the wordline acting as word selection line. The match
operation is done using bit and bit_b as search data with output on the match line
(ML).
6.4.2.3 Current-Mode WTA Logic
The WTA logic for this memory can be implemented using current comparison.
Figure 6.26 shows an example of a standard WTA circuit where input currents
I 1 to I N represent BL read currents mirrored in the WTA circuit. An application
for current-mode WTA is an associative memory using 10T-NOR CAM bitcells as
shown in Fig. 6.27.
97
in a single column to perform two parallel search operations and one- or twoword write at any given time. BLRs are used as match lines with active pull-ups.
WTA comparison logic is used to compare all match lines in order to find the
closest match. Comparison provides one-cold encoded output, which is followed
by sense amplifiers to fully resolve the matching and provide digital outputs. The
same WTA comparison logic shown in Fig. 6.17 can be used for TFET memories
as well. In order to achieve the maximum discharge current on BLR for the closest
match, Fig. 6.21, it is necessary to get the maximum number of zeroes connected
to BLR during a match, see the detailed explanation in Sect. 6.4.1 above. In case of
mismatch, the bitcell node storing a “1” is connected to bitline BLR, therefore, there
is no BLR discharge through mismatched bits. In case of a match BLR is discharged
either through node V1 or node V2 depending on the selected wordline. In case
of a partial match BLR discharges through a single or multiple bitcells depending
on the number of matching bits. In order to find the closest match, the maximum
BLR discharge current through bitcells with bitline pull-up switched ON needs to
be detected. The BLR voltage will be decided by the ratio of the resistance of BLR
pull-up and BLR discharge path through bitcells for matched bits. BLR1 and BLR2
are used to search simultaneously for two words, one from the upper half of the
column and the other from the lower half (see Fig. 6.21), respectively. The two BLRs
work identically as described above, each with its own WTA logic block.
The write operation is performed in a similar way to the SRAM, except that
the BLW for the selected word, i.e. one column, is activated by pulling it low and
selecting WL’s according to the data. Two-word write is possible by activating WL’s
for both sets of words and pulling BLW low.
6.4.2.2 Associative Memory Using Standard 10T-NOR CAM Bitcell
The proposed associative memory can also be implemented in CMOS using a
standard 10T-NOR CAM bitcell shown in Fig. 6.23. Similar comparison logic as
the one shown in Fig. 6.17, is implemented on match lines with match precharge
ON during search operation. The basic architecture is shown in Fig. 6.24 and overall
memory organization is shown in Fig. 6.25. Write is performed using bit and bit_b
lines as data lines with the wordline acting as word selection line. The match
operation is done using bit and bit_b as search data with output on the match line
(ML).
6.4.2.3 Current-Mode WTA Logic
The WTA logic for this memory can be implemented using current comparison.
Figure 6.26 shows an example of a standard WTA circuit where input currents
I 1 to I N represent BL read currents mirrored in the WTA circuit. An application
for current-mode WTA is an associative memory using 10T-NOR CAM bitcells as
shown in Fig. 6.27.