94
6 Content-Addressable Memories
PRE_WTA
PRE_WTA_N
BL[0]
VDD
GND
VC
WTA[0]
dout_wta[0]
GND
dout_wta[1]
dout_wta[N-1]
Sense Amplifiers
(Single ended)
N bit output (one-cold encoded/one-hot encoded)
Fig. 6.18 Winner-take-all logic for one memory bank; one WTA per column
Wordlines
BL[0]
Dout_wta[0]
BL[1]
BL[2]
Dout_wta[1]
Dout_wta[2]
SA outputs
(‘0’ for winner, rest all ‘1’s)
µ
µ
µ
µ
µ
µ
µ
Fig. 6.19 Search operation waveform, simulation condition (mismatch): Col[0]-4 bit, Col[1]-3
bit, Col[2]-1 bit
6 Content-Addressable Memories
PRE_WTA
PRE_WTA_N
BL[0]
VDD
GND
VC
WTA[0]
dout_wta[0]
GND
dout_wta[1]
dout_wta[N-1]
Sense Amplifiers
(Single ended)
N bit output (one-cold encoded/one-hot encoded)
Fig. 6.18 Winner-take-all logic for one memory bank; one WTA per column
Wordlines
BL[0]
Dout_wta[0]
BL[1]
BL[2]
Dout_wta[1]
Dout_wta[2]
SA outputs
(‘0’ for winner, rest all ‘1’s)
µ
µ
µ
µ
µ
µ
µ
Fig. 6.19 Search operation waveform, simulation condition (mismatch): Col[0]-4 bit, Col[1]-3
bit, Col[2]-1 bit