6.4 Associative Memory Architecture
93
Table 6.5 Signal voltages during Search
Active cells (search data =“0”)
Active cells (search data =“1”)
BL (pull-up ON)
1.0 V
1.0 V
WL1
0 V
1.0 V
WL2
1.0 V
0 V
VDD
1.0 V
1.0 V
GND
0.5 V (VDD/2)
0.5 V (VDD/2)
drive read-assist (WL under drive-RA), can be used to improve the read stability
of the cell.
During search the highest BL discharge current, i.e. the lowest BL voltage, is
present on the word/column, which has data closest to the search data, i.e. the
highest number of “0”s read. The WTA logic can be implemented to compare read
currents on BL or the corresponding BL voltages. Figure 6.17 shows a voltagecomparison WTA circuit, where the BL voltage for different columns is compared
to find the lowest voltage. The BL voltage is decided by the ratio of pull-up current
to the total BL discharge current of BLs in the word/column. As shown in Fig. 6.17
BL voltages are compared by the WTA logic to generate a one-cold encoded
dout_wta[*] output.
The circuit operation is described as follows:
I bias sets the maximum current through the WTA logic of the entire array. For
each different BL voltage, each WTA, i.e. per BL, will intend to consume current.
By considering, for instance, the case in Fig. 6.17 with BL[0] going lower than
BL[1], V[0] goes higher than V[1] meaning the corresponding pull-down n-type
device is more conductive for column 0 than for column 1. As a result, the NMOS
on the left in column 0 has a higher V GS than the corresponding NMOS in column 1
and I[0] is higher than I[1] due to “vc” being set by I bias ; the corresponding output
dout_wta[0] will consume almost all I bias leaving other branches with almost zero
current. This results in dout_wta outputs going high for all the columns except the
one conducting the I bias current. Figure 6.18 shows the WTA logic for each memory
bank, one per column, and a common current source for the bank. Waveforms
for column 0, 1, and 2 are shown during search in Fig. 6.19 with 4, 3, and 1 bit
mismatches, respectively.
6.4.1.2 Write Operation
The write operation is the same as described in Sect. 6.3. During write BL of the
selected column/word is at “GND” and for every bit of the word either WL1 or WL2
is selected depending on the value to be written into the cell, “1” or “0,” respectively.
Except for the column to be written, all other columns are in HS mode with bitlines
(BL’s) placed at retention-mode voltage (V DD/2) and the virtual ground of bitcells
at V DD/2. This is done to reduce power consumption in HS columns even when
93
Table 6.5 Signal voltages during Search
Active cells (search data =“0”)
Active cells (search data =“1”)
BL (pull-up ON)
1.0 V
1.0 V
WL1
0 V
1.0 V
WL2
1.0 V
0 V
VDD
1.0 V
1.0 V
GND
0.5 V (VDD/2)
0.5 V (VDD/2)
drive read-assist (WL under drive-RA), can be used to improve the read stability
of the cell.
During search the highest BL discharge current, i.e. the lowest BL voltage, is
present on the word/column, which has data closest to the search data, i.e. the
highest number of “0”s read. The WTA logic can be implemented to compare read
currents on BL or the corresponding BL voltages. Figure 6.17 shows a voltagecomparison WTA circuit, where the BL voltage for different columns is compared
to find the lowest voltage. The BL voltage is decided by the ratio of pull-up current
to the total BL discharge current of BLs in the word/column. As shown in Fig. 6.17
BL voltages are compared by the WTA logic to generate a one-cold encoded
dout_wta[*] output.
The circuit operation is described as follows:
I bias sets the maximum current through the WTA logic of the entire array. For
each different BL voltage, each WTA, i.e. per BL, will intend to consume current.
By considering, for instance, the case in Fig. 6.17 with BL[0] going lower than
BL[1], V[0] goes higher than V[1] meaning the corresponding pull-down n-type
device is more conductive for column 0 than for column 1. As a result, the NMOS
on the left in column 0 has a higher V GS than the corresponding NMOS in column 1
and I[0] is higher than I[1] due to “vc” being set by I bias ; the corresponding output
dout_wta[0] will consume almost all I bias leaving other branches with almost zero
current. This results in dout_wta outputs going high for all the columns except the
one conducting the I bias current. Figure 6.18 shows the WTA logic for each memory
bank, one per column, and a common current source for the bank. Waveforms
for column 0, 1, and 2 are shown during search in Fig. 6.19 with 4, 3, and 1 bit
mismatches, respectively.
6.4.1.2 Write Operation
The write operation is the same as described in Sect. 6.3. During write BL of the
selected column/word is at “GND” and for every bit of the word either WL1 or WL2
is selected depending on the value to be written into the cell, “1” or “0,” respectively.
Except for the column to be written, all other columns are in HS mode with bitlines
(BL’s) placed at retention-mode voltage (V DD/2) and the virtual ground of bitcells
at V DD/2. This is done to reduce power consumption in HS columns even when