3 Materials and Processing of TSV
69
Components and Technology Conference, 26–29 May 2009 (IEEE, San Diego, CA, 2009), p.
1159
42. P. Shi, J. Enloe, R. van den Boom, B. Sapp, Direct copper electrodeposition on a chemical vapordeposited Ruthenium seed layer for through-silicon vias, in IITC: International Interconnect
Technology Conference, 4–6 June 2012 (IEEE, San Jose, CA, 2012), p. 1
43. M.J. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. Engelmann, O. Ehrmann, A. Uhlig,
B. Michel, H. Reichl, High aspect ratio TSV copper filling with different seed layers, in ECTC:
Electronic Components and Technology Conference, 27–30 May 2008 (IEEE, Lake Buena
Vista, FL, 2008), p. 563
44. V.S. Rao, S.W. Ho, W.S.V. Lee, H.Y. Li, E. Liao, R. Nagarajan, T.C. Chai, X. Zhang, P.
Damaruganath, TSV interposer fabrication for 3D IC packaging, in EPTC’09: Electronics
Packaging Technology Conference, 9–11 Dec 2009 (IEEE, Singapore, 2009). p. 431
45. Y. Au, Q.M. Wang, H. Li, J.S.M. Lehn, D.V. Shenai, R.G. Gordon, Vapor deposition of highly
conformal copper seed layers for plating through-silicon vias (TSVs). J. Electrochem. Soc.
159, D382–D385 (2012)
46. P.H. Haumesser, L.A. Roule, S. Maitrejean, G. Passemard, Seed enhancement: a bridging
technology. Future Fab. Int. 19, 81–83 (2005)
47. K.J. Ganesh, A.D. Darbal, S. Rajasekhara, Effect of downscaling nano-copper interconnects
on the microstructure revealed by high resolution TEM-orientation-mapping. Nanotechnology
23, 135702 (2012)
48. B. Horvath, J. Kawakita, T. Chikyow, Through silicon via filling methods with metal/polymer
composite for three-dimensional LSI. Jpn. J. Appl. Phys. 53, 06JH01 (2014)
49. P. Dixit, T. Vehmas, S. Vahanen, P. Monnoyer, K. Henttinen, Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias. J. Micromech. Microeng.
22, 055021 (2012)
50. C.-F. Hsu, W.-P. Dow, H.-C. Chang, W.-Y. Chiu, Optimization of the copper plating process
using the Taguchi experimental design method: I. Microvia filling by copper plating using dual
leverlers. J. Electrochem. Soc. 162, D525–D530 (2015)
51. G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J.F. Lugand, R. Anciant, N. Sillon, Through silicon via technology using tungsten metallization, in Conference IC Design &
Technology, 2–4 May 2011 (IEEE, Kaohsiung, 2011), p. 1
52. T.P. Moffat, D. Josell, Extreme bottom-up superfilling of through-silicon-vias by damascene
processing: suppressor disruption, positive feedback and Turing patterns. J. Electrochem. Soc.
159, D208–D216 (2012)
53. J. Dukovic, S. Ramaswami, S. Pamarthy, R. Yalamanchili, N. Rajagopalan, K. Sapre, Z. Cao,
T. Ritzdorf, Y. Wang, B. Eaton, R. Ding, M. Hernandez, M. Naik, D. Mao, J. Tseng, D. Cui,
G. Mori, P. Fulmer, K. Sirajuddin, J. Hua, S. Xia, D. Erickson, R. Beica, E. Young, P. Kusler,
R. Kulzer, S. Oemardani, H. Dai, X. Xu, M. Okazaki, K. Dotan, C. Yu, C. Lazik, J. Tran,
L. Luo, L, Through-silicon-via technology for 3D integration, in IEEE International Memory
Workshop, 16–19 May 2010 (IEEE, Seoul, 2010), p 1
54. D. Smith, S. Singh, Y. Ramnath, M. Rabie, D. Zhang, L. England, TSV residual Cu step height
analysis by white light interferometry for 3D integration, in ECTC: Electronic Components
and Technology Conference, 26–29 May 2015 (IEEE, San Diego, CA, 2015), p. 578
55. R.L. Rhoades, Overview of CMP for TSV applications (2013). http://www.entrepix.com/docs/
papers-and-presentations/Rhoades-CMP-for-TSV-AVS-June2013-shareable.pdf. Accessed
21 June 2016
56. S.W. Yoon, D.J. Na, K.T. Kang, W.K. Choi, C.B. Yong, Y.C. Kim, P.C. Marimuthu,
TSV MEOL (Mid-End-Of-Line) and its assembly/packaging technology for 3D/2.5D
solutions, in ICEP-IAAC: Joint Conference of International Conference on Electronics Packaging and IMAPS All Asia Conference, 17–20 April 2012, Tokyo,
Japan (2012). http://www.statschippac.com/~/media/Files/DocLibrary/whitepapers/2012/
STATSChipPAC_ICEP2012_TSV_MEOL_and_Pkg.ashx. Accessed 21 June 2016
57. A. Heryanto, W.N. Putra, A. Trigg, S. Gao, W.S. Kwon, F.X. Che, X.F. Ang, J. Wei, R.I.
Made, C.L. Gan, K.L. Pey, Effect of copper TSV annealing on via protrusion for TSV wafer
fabrication. J. Electron. Mater. 41, 2533–2542 (2012)
69
Components and Technology Conference, 26–29 May 2009 (IEEE, San Diego, CA, 2009), p.
1159
42. P. Shi, J. Enloe, R. van den Boom, B. Sapp, Direct copper electrodeposition on a chemical vapordeposited Ruthenium seed layer for through-silicon vias, in IITC: International Interconnect
Technology Conference, 4–6 June 2012 (IEEE, San Jose, CA, 2012), p. 1
43. M.J. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. Engelmann, O. Ehrmann, A. Uhlig,
B. Michel, H. Reichl, High aspect ratio TSV copper filling with different seed layers, in ECTC:
Electronic Components and Technology Conference, 27–30 May 2008 (IEEE, Lake Buena
Vista, FL, 2008), p. 563
44. V.S. Rao, S.W. Ho, W.S.V. Lee, H.Y. Li, E. Liao, R. Nagarajan, T.C. Chai, X. Zhang, P.
Damaruganath, TSV interposer fabrication for 3D IC packaging, in EPTC’09: Electronics
Packaging Technology Conference, 9–11 Dec 2009 (IEEE, Singapore, 2009). p. 431
45. Y. Au, Q.M. Wang, H. Li, J.S.M. Lehn, D.V. Shenai, R.G. Gordon, Vapor deposition of highly
conformal copper seed layers for plating through-silicon vias (TSVs). J. Electrochem. Soc.
159, D382–D385 (2012)
46. P.H. Haumesser, L.A. Roule, S. Maitrejean, G. Passemard, Seed enhancement: a bridging
technology. Future Fab. Int. 19, 81–83 (2005)
47. K.J. Ganesh, A.D. Darbal, S. Rajasekhara, Effect of downscaling nano-copper interconnects
on the microstructure revealed by high resolution TEM-orientation-mapping. Nanotechnology
23, 135702 (2012)
48. B. Horvath, J. Kawakita, T. Chikyow, Through silicon via filling methods with metal/polymer
composite for three-dimensional LSI. Jpn. J. Appl. Phys. 53, 06JH01 (2014)
49. P. Dixit, T. Vehmas, S. Vahanen, P. Monnoyer, K. Henttinen, Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias. J. Micromech. Microeng.
22, 055021 (2012)
50. C.-F. Hsu, W.-P. Dow, H.-C. Chang, W.-Y. Chiu, Optimization of the copper plating process
using the Taguchi experimental design method: I. Microvia filling by copper plating using dual
leverlers. J. Electrochem. Soc. 162, D525–D530 (2015)
51. G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J.F. Lugand, R. Anciant, N. Sillon, Through silicon via technology using tungsten metallization, in Conference IC Design &
Technology, 2–4 May 2011 (IEEE, Kaohsiung, 2011), p. 1
52. T.P. Moffat, D. Josell, Extreme bottom-up superfilling of through-silicon-vias by damascene
processing: suppressor disruption, positive feedback and Turing patterns. J. Electrochem. Soc.
159, D208–D216 (2012)
53. J. Dukovic, S. Ramaswami, S. Pamarthy, R. Yalamanchili, N. Rajagopalan, K. Sapre, Z. Cao,
T. Ritzdorf, Y. Wang, B. Eaton, R. Ding, M. Hernandez, M. Naik, D. Mao, J. Tseng, D. Cui,
G. Mori, P. Fulmer, K. Sirajuddin, J. Hua, S. Xia, D. Erickson, R. Beica, E. Young, P. Kusler,
R. Kulzer, S. Oemardani, H. Dai, X. Xu, M. Okazaki, K. Dotan, C. Yu, C. Lazik, J. Tran,
L. Luo, L, Through-silicon-via technology for 3D integration, in IEEE International Memory
Workshop, 16–19 May 2010 (IEEE, Seoul, 2010), p 1
54. D. Smith, S. Singh, Y. Ramnath, M. Rabie, D. Zhang, L. England, TSV residual Cu step height
analysis by white light interferometry for 3D integration, in ECTC: Electronic Components
and Technology Conference, 26–29 May 2015 (IEEE, San Diego, CA, 2015), p. 578
55. R.L. Rhoades, Overview of CMP for TSV applications (2013). http://www.entrepix.com/docs/
papers-and-presentations/Rhoades-CMP-for-TSV-AVS-June2013-shareable.pdf. Accessed
21 June 2016
56. S.W. Yoon, D.J. Na, K.T. Kang, W.K. Choi, C.B. Yong, Y.C. Kim, P.C. Marimuthu,
TSV MEOL (Mid-End-Of-Line) and its assembly/packaging technology for 3D/2.5D
solutions, in ICEP-IAAC: Joint Conference of International Conference on Electronics Packaging and IMAPS All Asia Conference, 17–20 April 2012, Tokyo,
Japan (2012). http://www.statschippac.com/~/media/Files/DocLibrary/whitepapers/2012/
STATSChipPAC_ICEP2012_TSV_MEOL_and_Pkg.ashx. Accessed 21 June 2016
57. A. Heryanto, W.N. Putra, A. Trigg, S. Gao, W.S. Kwon, F.X. Che, X.F. Ang, J. Wei, R.I.
Made, C.L. Gan, K.L. Pey, Effect of copper TSV annealing on via protrusion for TSV wafer
fabrication. J. Electron. Mater. 41, 2533–2542 (2012)