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21. B. Wu, A. Kumar, S. Pamarthy, High aspect ratio silicon etch: a review. J. Appl. Phys. 108,
051101 (2010)
22. D. Gerke, NASA 2009 Body of Knowledge (BoK): Through-Silicon Via Technology (JPL Publication 09-28, Jet Propulsion Laboratory, Pasadena, CA, 2009)
23. R. Landgraf, R. Rieske, A.N. Danilewsky, K.J. Wolter, Laser drilled through silicon vias: crystal
defect analysis by synchrotron X-ray topography, in ESTC: 2nd Electronics System-Integration
Technology Conference, Greenwich, UK, 1–4 Sept 2008 (IEEE, 2008), p. 1023
24. Industrial laser application note: laser drilling of through silicon vias (TSV). http://www.
spectra-physics.com/applications/application-notes/laser-drilling-of-through-silicon-viastsv. Accessed 21 June 2016
25. Y.H. Lee, K.J. Choi, Analysis of silicon via hole drilling for wafer level chip stacking by UV
laser. Int. J. Precis. Eng. Manuf. 11, 501–507 (2010)
26. A. Polyakov, T. Grob, R.A. Hovenkamp, H.J. Kettelarij, I. Eidner, M.A. de Samber, M. Bartek,
J.N. Burghartz, Comparison of via-fabrication techniques for through-wafer electrical interconnect applications, in ECTC: Electronic Components and Technology Conference, 1–4 June
2004 (IEEE, 2004), p. 1466
27. S.P. Lee, H.-W. Kang, S.-J. Lee, I.H. Lee, T.J. Ko, D.-W. Cho, Development of rapid mask
fabrication technology for micro-abrasive jet machining. J Mech. Sci. Technol. 22, 2190–2196
(2008)
28. S.H. Kim et al., (110) Silicon etching for high aspect ratio comb structures, in ETFA’97:
Proceedings of Emerging Technologies and Fatory Automation, 9–12 Sept 1997 (Los Angeles,
IEEE, CA, 1997), p. 248
29. G.T.A. Kovacs, N.I. Maluf, K.E. Petersen, Bulk micromachining of silicon. Proc. IEEE 86,
1536–1551 (1998)
30. M.J. Archer, F.S. Ligler, Fabrication and characterization of silicon micro-funnels and tapered
micro-channels for stochastic sensing applications. Sensors 8, 3848–3872 (2008)
31. S. Aachboun, P. Ranson, Deep anisotropic etching of silicon. J. Vac. Sci. Technol. A 17, 2270–
2273 (1999)
32. F. Laermer, A. Schilp, Method of anisotropically etching silicon. US Patent US5501893 A
(1996)
33. M.J. Madou, Fundamentals of Microfabrication: The Science of Miniaturization, 2nd edn.
(CRC Press, Boca Raton, 2002)
34. S.-B. Jo, M.-W. Lee, S.-G. Lee, E.-H. Lee, S.-G. Park, O B.-H., Characterization of a modified
Bosch-type process for silicon mold fabrication. J. Vac. Sci. Technol. A 23, 905–910 (2005)
35. P. Nallan, A. Khan, S. Pamarthy, S.T. Hsu, A. Kumar, Advanced deep silicon etching for deep
trench isolation, optical components and micro-machining applications, in ET Conference
Proceedings (Applied Materials Internal Publication, 2001)
36. M.J. Walker, Comparison of Bosch and cryogenic processes for patterning high aspect ratio
features in silicon. Proc. SPIE 4407, 89–99 (2001)
37. I.R. Johnston, H. Ashraf, J.K. Bhardwaj, J. Hopkins, A.M. Hynes, G. Nicholls, S.A. McAuley, S.
Hall, L. Atabo, G.R. Bogart, A. Kornblit, A.E. Novembre, Etching 200-mm diameter SCALPEL
masks with the ASE process. Proc. SPIE 3997, 184–193 (2000)
38. R. Nagarajan, L. Ebin, D. Lee, C.S. Soh, K. Prasad, N. Balasubramanian, Development of a
novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated
systems, in ECTC: Electronic Components and Technology Conference, 30 May–2 June 2006
(IEEE, San Diego, CA, 2006), p. 383
39. J.-H. Lai, H.S. Yang, H. Chen, C.R. King, J. Zaveri, R. Ravindran, M.S. Bakir, A ‘mesh’
seed layer for improved through-silicon-via fabrication. J. Micromech. Microeng. 20, 025016
(2010)
40. M. Miao, Y. Zhu, M. Ji, J. Ma, X. Sun, Y. Jin, Bottom-up filling of through silicon via (TSV)
with Parylene as sidewall protection layer, in EPTC’09: Electronics Packaging Technology
Conference, 9–11 Dec 2009 (IEEE, Singapore, 2009), p. 442
41. D.S. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, B. Swinnen, Scalable through silicon
via with polymer deep trench isolation for 3D wafer level packaging, in ECTC: Electronic
P. Kumar et al.
21. B. Wu, A. Kumar, S. Pamarthy, High aspect ratio silicon etch: a review. J. Appl. Phys. 108,
051101 (2010)
22. D. Gerke, NASA 2009 Body of Knowledge (BoK): Through-Silicon Via Technology (JPL Publication 09-28, Jet Propulsion Laboratory, Pasadena, CA, 2009)
23. R. Landgraf, R. Rieske, A.N. Danilewsky, K.J. Wolter, Laser drilled through silicon vias: crystal
defect analysis by synchrotron X-ray topography, in ESTC: 2nd Electronics System-Integration
Technology Conference, Greenwich, UK, 1–4 Sept 2008 (IEEE, 2008), p. 1023
24. Industrial laser application note: laser drilling of through silicon vias (TSV). http://www.
spectra-physics.com/applications/application-notes/laser-drilling-of-through-silicon-viastsv. Accessed 21 June 2016
25. Y.H. Lee, K.J. Choi, Analysis of silicon via hole drilling for wafer level chip stacking by UV
laser. Int. J. Precis. Eng. Manuf. 11, 501–507 (2010)
26. A. Polyakov, T. Grob, R.A. Hovenkamp, H.J. Kettelarij, I. Eidner, M.A. de Samber, M. Bartek,
J.N. Burghartz, Comparison of via-fabrication techniques for through-wafer electrical interconnect applications, in ECTC: Electronic Components and Technology Conference, 1–4 June
2004 (IEEE, 2004), p. 1466
27. S.P. Lee, H.-W. Kang, S.-J. Lee, I.H. Lee, T.J. Ko, D.-W. Cho, Development of rapid mask
fabrication technology for micro-abrasive jet machining. J Mech. Sci. Technol. 22, 2190–2196
(2008)
28. S.H. Kim et al., (110) Silicon etching for high aspect ratio comb structures, in ETFA’97:
Proceedings of Emerging Technologies and Fatory Automation, 9–12 Sept 1997 (Los Angeles,
IEEE, CA, 1997), p. 248
29. G.T.A. Kovacs, N.I. Maluf, K.E. Petersen, Bulk micromachining of silicon. Proc. IEEE 86,
1536–1551 (1998)
30. M.J. Archer, F.S. Ligler, Fabrication and characterization of silicon micro-funnels and tapered
micro-channels for stochastic sensing applications. Sensors 8, 3848–3872 (2008)
31. S. Aachboun, P. Ranson, Deep anisotropic etching of silicon. J. Vac. Sci. Technol. A 17, 2270–
2273 (1999)
32. F. Laermer, A. Schilp, Method of anisotropically etching silicon. US Patent US5501893 A
(1996)
33. M.J. Madou, Fundamentals of Microfabrication: The Science of Miniaturization, 2nd edn.
(CRC Press, Boca Raton, 2002)
34. S.-B. Jo, M.-W. Lee, S.-G. Lee, E.-H. Lee, S.-G. Park, O B.-H., Characterization of a modified
Bosch-type process for silicon mold fabrication. J. Vac. Sci. Technol. A 23, 905–910 (2005)
35. P. Nallan, A. Khan, S. Pamarthy, S.T. Hsu, A. Kumar, Advanced deep silicon etching for deep
trench isolation, optical components and micro-machining applications, in ET Conference
Proceedings (Applied Materials Internal Publication, 2001)
36. M.J. Walker, Comparison of Bosch and cryogenic processes for patterning high aspect ratio
features in silicon. Proc. SPIE 4407, 89–99 (2001)
37. I.R. Johnston, H. Ashraf, J.K. Bhardwaj, J. Hopkins, A.M. Hynes, G. Nicholls, S.A. McAuley, S.
Hall, L. Atabo, G.R. Bogart, A. Kornblit, A.E. Novembre, Etching 200-mm diameter SCALPEL
masks with the ASE process. Proc. SPIE 3997, 184–193 (2000)
38. R. Nagarajan, L. Ebin, D. Lee, C.S. Soh, K. Prasad, N. Balasubramanian, Development of a
novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated
systems, in ECTC: Electronic Components and Technology Conference, 30 May–2 June 2006
(IEEE, San Diego, CA, 2006), p. 383
39. J.-H. Lai, H.S. Yang, H. Chen, C.R. King, J. Zaveri, R. Ravindran, M.S. Bakir, A ‘mesh’
seed layer for improved through-silicon-via fabrication. J. Micromech. Microeng. 20, 025016
(2010)
40. M. Miao, Y. Zhu, M. Ji, J. Ma, X. Sun, Y. Jin, Bottom-up filling of through silicon via (TSV)
with Parylene as sidewall protection layer, in EPTC’09: Electronics Packaging Technology
Conference, 9–11 Dec 2009 (IEEE, Singapore, 2009), p. 442
41. D.S. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, B. Swinnen, Scalable through silicon
via with polymer deep trench isolation for 3D wafer level packaging, in ECTC: Electronic