3 Materials and Processing of TSV
67
References
1. E. Beyne, Through-silicon via technology for 3D IC, in Ultra-Thin Chip Technology and
Applications, ed. by J.N. Burghartz (Springer, New York, 2011)
2. M. Stucchi, G. Katti, D. Velenis, TSV characterization and modeling, in Three Dimensional
System Integration: IC Stacking Process and Design, ed. by A. Papanikolaou, D. Soudris, R.
Radojcic (Springer, New York, 2011)
3. P.S. Andry, C.K. Tsang, B.C. Webb, E.J. Sprogis, S.L. Wright, B. Dang, D.G. Manzer, Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. IBM
J. Res. Dev. 52, 571–581 (2008)
4. Z. Xu, J.Q. Lu, High-speed design and broadband modeling of through-strata-vias (TSVs) in
3D integration. IEEE Trans. Compon. Pack. Manuf. Technol. 1, 154–162 (2011)
5. J.Q. Lu, Advances in materials and processes for 3D-TSV integration. ECS Trans. 45, 119–129
(2012)
6. A. Tsukada, R. Sato, S. Sekine, R. Kimura, K. Kishi, Y. Sato, Y. Iwata, H. Murata, Study on
TSV with new filling method and alloy for advanced 3D-SiP, in ECTC: Electronic Components
and Technology Conference, 31 May–3 June 2011 (IEEE, Lake Buena Vista, FL, 2011), p. 1981
7. R. Sato, A. Tsukada, Y. Sato, Y. Iwata, H. Murata, S. Sekine, R. Kimura, K. Kishi, Study on
high performance and productivity of TSV’s with new filling method and alloy for advanced
3D-SiP, in 3DIC: International 3D Systems Integration Conference, 31 Jan–2 Feb 2012 (IEEE,
Osaka, 2012), p. 1
8. A. Horibe, K. Sueoka, T. Aoki, K. Toriyama, K. Okamoto, S. Kohara, H. Mori, Y. Orii, Through
silicon via process for effective multi-wafer integration, in ECTC: Electronic Components and
Technology Conference, 26–29 May 2015 (IEEE, San Diego, CA, 2015), p. 1808
9. M. Bouchoucha, L.L. Chapelon, P. Chausse, S. Moreau, N. Sillon, Through silicon via polymer
filling for 3D-WLP applications, in ESTC: Electronic System-Integration Technology Conference, 13–16 Sept 2010 (IEEE, Berlin, 2010), p. 1
10. A. Peic, Lithography process innovations for 2.5/3D Part 1: alleviating TSV stress
(2014). http://www.3dincites.com/2014/08/lithography-process-innovations-for-2-53d-part1-alleviating-tsv-stress/. Accessed 21 June 2016
11. L. Zhu, D.W. Hess, C.P. Wong, Carbon nanotube electrical and thermal properties and applications for interconnects, in Integrated Interconnect Technologies for 3D Nanoelectronic Systems,
ed. by M.S. Bakir, J.D. Meindl (Artech House, Norwood, MA, 2009)
12. D. Jiang, W. Mu, S. Chen, Y. Fu, K. Jeppson, J. Liu, Vertically stacked carbon nanotube-based
interconnects for through silicon via application. IEEE Electron. Dev. Lett. 36, 499–501 (2015)
13. J.U. Knickerbocker, P.S. Andry, B. Dang et al., Three dimensional silicon integration. IBM J.
Res. Dev. 52, 553–569 (2008)
14. J.Q. Lu, 3-D hyperintegration and packaging technologies for micro-nano systems. Proc. IEEE
97, 18–30 (2009)
15. M. Koyanagi, T. Fkushima, T. Tanaka, High-density through silicon vias for 3-D LSIs. Proc.
IEEE 97, 49–59 (2009)
16. S. Spiesshoefer, Z. Rahman, G. Vangara, S. Polamreddy, S. Burkett, L. Schaper, Process integration for through-silicon vias. J. Vac. Sci. Technol. A 23, 824–829 (2005)
17. R. Nagarajan, K. Prasad, L. Ebin, B. Narayanan, Development of dual-etch via tapering process
for through-silicon interconnection. Sens. Actuat. A 139, 323–329 (2007)
18. R. Li, Y. Lamy, W.F.A. Besling, F. Roozeboom, P.M. Sarro, Continuous deep reactive ion
etching of tapered via holes for three-dimensional integration. J. Micromech. Microeng. 18,
125023 (2008)
19. C. Okoro, K. Vanstreels, R. Labie, O. Luhn, B. Vandevelde, B. Verlinden, D. Vandepitte, Influence of annealing conditions on the mechanical and microstructural behavior of electroplated
Cu-TSV. J. Micromech. Microeng. 20, 045032 (2010)
20. N. Ranganathan, L. Ebin, L. Linn, L.W.S. Vincent, O.K. Navas, V. Kripesh, N. Balasubramanian, Integration of high aspect ratio tapered silicon via for silicon carrier fabrication. IEEE
Trans. Adv. Pack. 32, 62–71 (2009)
67
References
1. E. Beyne, Through-silicon via technology for 3D IC, in Ultra-Thin Chip Technology and
Applications, ed. by J.N. Burghartz (Springer, New York, 2011)
2. M. Stucchi, G. Katti, D. Velenis, TSV characterization and modeling, in Three Dimensional
System Integration: IC Stacking Process and Design, ed. by A. Papanikolaou, D. Soudris, R.
Radojcic (Springer, New York, 2011)
3. P.S. Andry, C.K. Tsang, B.C. Webb, E.J. Sprogis, S.L. Wright, B. Dang, D.G. Manzer, Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. IBM
J. Res. Dev. 52, 571–581 (2008)
4. Z. Xu, J.Q. Lu, High-speed design and broadband modeling of through-strata-vias (TSVs) in
3D integration. IEEE Trans. Compon. Pack. Manuf. Technol. 1, 154–162 (2011)
5. J.Q. Lu, Advances in materials and processes for 3D-TSV integration. ECS Trans. 45, 119–129
(2012)
6. A. Tsukada, R. Sato, S. Sekine, R. Kimura, K. Kishi, Y. Sato, Y. Iwata, H. Murata, Study on
TSV with new filling method and alloy for advanced 3D-SiP, in ECTC: Electronic Components
and Technology Conference, 31 May–3 June 2011 (IEEE, Lake Buena Vista, FL, 2011), p. 1981
7. R. Sato, A. Tsukada, Y. Sato, Y. Iwata, H. Murata, S. Sekine, R. Kimura, K. Kishi, Study on
high performance and productivity of TSV’s with new filling method and alloy for advanced
3D-SiP, in 3DIC: International 3D Systems Integration Conference, 31 Jan–2 Feb 2012 (IEEE,
Osaka, 2012), p. 1
8. A. Horibe, K. Sueoka, T. Aoki, K. Toriyama, K. Okamoto, S. Kohara, H. Mori, Y. Orii, Through
silicon via process for effective multi-wafer integration, in ECTC: Electronic Components and
Technology Conference, 26–29 May 2015 (IEEE, San Diego, CA, 2015), p. 1808
9. M. Bouchoucha, L.L. Chapelon, P. Chausse, S. Moreau, N. Sillon, Through silicon via polymer
filling for 3D-WLP applications, in ESTC: Electronic System-Integration Technology Conference, 13–16 Sept 2010 (IEEE, Berlin, 2010), p. 1
10. A. Peic, Lithography process innovations for 2.5/3D Part 1: alleviating TSV stress
(2014). http://www.3dincites.com/2014/08/lithography-process-innovations-for-2-53d-part1-alleviating-tsv-stress/. Accessed 21 June 2016
11. L. Zhu, D.W. Hess, C.P. Wong, Carbon nanotube electrical and thermal properties and applications for interconnects, in Integrated Interconnect Technologies for 3D Nanoelectronic Systems,
ed. by M.S. Bakir, J.D. Meindl (Artech House, Norwood, MA, 2009)
12. D. Jiang, W. Mu, S. Chen, Y. Fu, K. Jeppson, J. Liu, Vertically stacked carbon nanotube-based
interconnects for through silicon via application. IEEE Electron. Dev. Lett. 36, 499–501 (2015)
13. J.U. Knickerbocker, P.S. Andry, B. Dang et al., Three dimensional silicon integration. IBM J.
Res. Dev. 52, 553–569 (2008)
14. J.Q. Lu, 3-D hyperintegration and packaging technologies for micro-nano systems. Proc. IEEE
97, 18–30 (2009)
15. M. Koyanagi, T. Fkushima, T. Tanaka, High-density through silicon vias for 3-D LSIs. Proc.
IEEE 97, 49–59 (2009)
16. S. Spiesshoefer, Z. Rahman, G. Vangara, S. Polamreddy, S. Burkett, L. Schaper, Process integration for through-silicon vias. J. Vac. Sci. Technol. A 23, 824–829 (2005)
17. R. Nagarajan, K. Prasad, L. Ebin, B. Narayanan, Development of dual-etch via tapering process
for through-silicon interconnection. Sens. Actuat. A 139, 323–329 (2007)
18. R. Li, Y. Lamy, W.F.A. Besling, F. Roozeboom, P.M. Sarro, Continuous deep reactive ion
etching of tapered via holes for three-dimensional integration. J. Micromech. Microeng. 18,
125023 (2008)
19. C. Okoro, K. Vanstreels, R. Labie, O. Luhn, B. Vandevelde, B. Verlinden, D. Vandepitte, Influence of annealing conditions on the mechanical and microstructural behavior of electroplated
Cu-TSV. J. Micromech. Microeng. 20, 045032 (2010)
20. N. Ranganathan, L. Ebin, L. Linn, L.W.S. Vincent, O.K. Navas, V. Kripesh, N. Balasubramanian, Integration of high aspect ratio tapered silicon via for silicon carrier fabrication. IEEE
Trans. Adv. Pack. 32, 62–71 (2009)