3 Materials and Processing of TSV
65
Fig. 3.13 Schematic of integration strategies via die-stacking and connecting with soldermicrobumps: (a) face-to-face, (b) back-to-back, and (c) face-to-back. (d) A redistribution layer
(RDL) is often utilized to connect dies, allowing TSVs to be placed at different locations from the
bond-pads
as illustrated in Fig. 3.13d. In addition to relaxing constraints associated with joint
spacing and size, multi-layered RDLs can reduce TSV-insertion losses, while also
improving signal transmission and reliability [60]. This strategy also obviates the
need for perfect alignment of pads connected to TSVs, allowing more flexibility in
soldering with very thin joints. Figure 3.14 shows cross-section of a device employing
face-to-back integration technique. Two key challenges during integration of two dies
are the handling of very thin wafers (<100 µm) and minimizing warpage during
assembly, respectively. To minimize these complications, the thinned Si wafer is
often temporarily attached to a glass or a thick wafer using curable epoxy, high
temperature adhesives or sometimes, by using electrostatic bonding. However, for
electrostatic bonding, the surfaces of the glass plate and the Si wafer need to be be
very smooth (<10 nm roughness) and clean. In addition, since electrostatic bonding
is performed at moderately high temperatures (>300
◦ C), a glass with CTE similar
to that of Si should be used.
65
Fig. 3.13 Schematic of integration strategies via die-stacking and connecting with soldermicrobumps: (a) face-to-face, (b) back-to-back, and (c) face-to-back. (d) A redistribution layer
(RDL) is often utilized to connect dies, allowing TSVs to be placed at different locations from the
bond-pads
as illustrated in Fig. 3.13d. In addition to relaxing constraints associated with joint
spacing and size, multi-layered RDLs can reduce TSV-insertion losses, while also
improving signal transmission and reliability [60]. This strategy also obviates the
need for perfect alignment of pads connected to TSVs, allowing more flexibility in
soldering with very thin joints. Figure 3.14 shows cross-section of a device employing
face-to-back integration technique. Two key challenges during integration of two dies
are the handling of very thin wafers (<100 µm) and minimizing warpage during
assembly, respectively. To minimize these complications, the thinned Si wafer is
often temporarily attached to a glass or a thick wafer using curable epoxy, high
temperature adhesives or sometimes, by using electrostatic bonding. However, for
electrostatic bonding, the surfaces of the glass plate and the Si wafer need to be be
very smooth (<10 nm roughness) and clean. In addition, since electrostatic bonding
is performed at moderately high temperatures (>300
◦ C), a glass with CTE similar
to that of Si should be used.