64
P. Kumar et al.
Fig. 3.12 Flow-process sequence for fabricating TSV assembly with respect to the fabrication of
FEOL and BEOL structures: (a) via-first, (b) via-middle and (c) via-last. It should be noted that
some of the sequences may interchange depending on the process optimization, for example, BEOL
structures may be formed before thinning the Si wafer in the via-first process sequence, etc
the choices for materials to be used as fillers, e.g., W and highly doped poly-silicon,
which have CTEs close to that of Si. On the other hand, the via-last process sequence
may avoid such thermal loading of TSV assemblies. Nevertheless, in addition to the
alignment issue, the via-last process also affords less process-flexibility due to the
presence of a large number of pre-formed structures (i.e., BEOL and FEOL) on the
Si wafer. Hence, fabricating vias with very small diameter (<5 µm) and very high
aspect ratios (>50) is relatively more difficult in via-last process sequence. Due to
the above limitations of the via-first and via-last processes, the via-middle process
sequence is often deemed to be advantageous and suitable for several applications.
3.4.2 Integration of Dies Comprising TSVs
Once a die comprising TSV structures is fabricated, it can then be integrated with
another die in the microelectronic device. As schematically shown in Fig. 3.13a–c,
one of the following three strategies can be used for integration [15]: (1) face-to-face
(F2F), where the front side, i.e., the side of the Si wafer which has the FEOL and
BEOL structures, of both dies face each other, (2) back-to-back (B2B), where the
back side of both dies face each other, and (3) face-to-back (F2B), where the front
side of one of the dies faces the back side of another die. In each of these integration
strategies, a joint between the properly aligned vias may be formed using solder
micro-bumps, often utilizing a bond-pad or copper pillar attached to the end of the
TSV. To minimize challenges associated with perfect alignment, and to fan out and/or
enlarge the inter-chip joints, a redistribution layer (RDL), comprising metal circuitry
(e.g., Cu) embedded in a dielectric layer (e.g., polyimide or benzocyclobutene), is
often utilized to re-route the electrical connections from the TSV to larger bond-pads,
P. Kumar et al.
Fig. 3.12 Flow-process sequence for fabricating TSV assembly with respect to the fabrication of
FEOL and BEOL structures: (a) via-first, (b) via-middle and (c) via-last. It should be noted that
some of the sequences may interchange depending on the process optimization, for example, BEOL
structures may be formed before thinning the Si wafer in the via-first process sequence, etc
the choices for materials to be used as fillers, e.g., W and highly doped poly-silicon,
which have CTEs close to that of Si. On the other hand, the via-last process sequence
may avoid such thermal loading of TSV assemblies. Nevertheless, in addition to the
alignment issue, the via-last process also affords less process-flexibility due to the
presence of a large number of pre-formed structures (i.e., BEOL and FEOL) on the
Si wafer. Hence, fabricating vias with very small diameter (<5 µm) and very high
aspect ratios (>50) is relatively more difficult in via-last process sequence. Due to
the above limitations of the via-first and via-last processes, the via-middle process
sequence is often deemed to be advantageous and suitable for several applications.
3.4.2 Integration of Dies Comprising TSVs
Once a die comprising TSV structures is fabricated, it can then be integrated with
another die in the microelectronic device. As schematically shown in Fig. 3.13a–c,
one of the following three strategies can be used for integration [15]: (1) face-to-face
(F2F), where the front side, i.e., the side of the Si wafer which has the FEOL and
BEOL structures, of both dies face each other, (2) back-to-back (B2B), where the
back side of both dies face each other, and (3) face-to-back (F2B), where the front
side of one of the dies faces the back side of another die. In each of these integration
strategies, a joint between the properly aligned vias may be formed using solder
micro-bumps, often utilizing a bond-pad or copper pillar attached to the end of the
TSV. To minimize challenges associated with perfect alignment, and to fan out and/or
enlarge the inter-chip joints, a redistribution layer (RDL), comprising metal circuitry
(e.g., Cu) embedded in a dielectric layer (e.g., polyimide or benzocyclobutene), is
often utilized to re-route the electrical connections from the TSV to larger bond-pads,