3 Materials and Processing of TSV
63
3.4 Flow Process for Fabricating TSVs and Integration
of Dies
A 3-D architectured microelectronic package comprising TSVs can be fabricated
using one of 9 different algorithms: three of these relate to the sequence in which
a TSV assembly is fabricated in the process-flow, whereas for each of these three
possibilities, there are three possible configurations in which the TSV containing
die can be integrated with other dies. In any of these algorithms, the basic steps for
fabricating TSV assemblies, consisting of etching Si, filling, and planarization and
thinning, remain the same as described in Sect. 3.3.
3.4.1 Sequence of Flow-Process
Based on the sequence of the process-flow, TSVs can be fabricated first, last or in
the middle, relative to the front end of line (FEOL) processes and the fabrication of
back end of line (BEOL) structures. Accordingly these are called via-first, via-last
and via-middle sequences, respectively [13]. As the names of these sequences suggest and as shown in Fig. 3.12, in the via-first and the via-last process sequences,
the TSV structures are fabricated before FEOL and after BEOL processes, respectively, whereas the TSV structures are fabricated after FEOL and before BEOL in
the via-middle process. In addition and as shown in Fig. 3.12, the Si wafer is etched
from the top (where the FEOL and BEOL structures reside) and thinned from the
bottom, after fabrication of TSV structures in the via-first and via-middle process
sequences. In contrast, in the via-last process, the Si wafer is thinned before fabrication of TSV structures, following which the via is etched from the bottom of
the wafer [33]. Therefore, maintaining proper alignment between the TSV and the
BEOL is challenging in the via-last process.
Another important aspect that affects the selection of the via-processing sequence
is the thermal budget during FEOL and BEOL processes. FEOL processing involves
oxidation and etching of Si and hence it is often conducted at high temperatures (>400
◦ C). BEOL processes, which comprise placing dielectrics, metal interconnects, etc., are generally conducted at relatively low temperatures (<400
◦ C),
although dielectric deposition temperatures can sometimes reach 425–450
◦ C. Hence,
selecting the sequence in which TSVs should be fabricated is important, and has to
be often optimized on a case-by-case basis. For example, fabricating TSV assemblies
in the via-first sequence is the easiest of all process sequences, as it allows working
on a pristine Si wafer with no other structure. However, since there may be considerable difference between the CTE of the metal filler and Si, the FEOL processing
may lead to the build up of significant thermal stresses in the structure, resulting
in metal pumping, interfacial sliding, fracture, and other reliability issues. In addition, certain filler metals, for example Cu, are difficult to use in the via-first process
sequence due to their very fast diffusivity into Si at high temperatures. This limits
63
3.4 Flow Process for Fabricating TSVs and Integration
of Dies
A 3-D architectured microelectronic package comprising TSVs can be fabricated
using one of 9 different algorithms: three of these relate to the sequence in which
a TSV assembly is fabricated in the process-flow, whereas for each of these three
possibilities, there are three possible configurations in which the TSV containing
die can be integrated with other dies. In any of these algorithms, the basic steps for
fabricating TSV assemblies, consisting of etching Si, filling, and planarization and
thinning, remain the same as described in Sect. 3.3.
3.4.1 Sequence of Flow-Process
Based on the sequence of the process-flow, TSVs can be fabricated first, last or in
the middle, relative to the front end of line (FEOL) processes and the fabrication of
back end of line (BEOL) structures. Accordingly these are called via-first, via-last
and via-middle sequences, respectively [13]. As the names of these sequences suggest and as shown in Fig. 3.12, in the via-first and the via-last process sequences,
the TSV structures are fabricated before FEOL and after BEOL processes, respectively, whereas the TSV structures are fabricated after FEOL and before BEOL in
the via-middle process. In addition and as shown in Fig. 3.12, the Si wafer is etched
from the top (where the FEOL and BEOL structures reside) and thinned from the
bottom, after fabrication of TSV structures in the via-first and via-middle process
sequences. In contrast, in the via-last process, the Si wafer is thinned before fabrication of TSV structures, following which the via is etched from the bottom of
the wafer [33]. Therefore, maintaining proper alignment between the TSV and the
BEOL is challenging in the via-last process.
Another important aspect that affects the selection of the via-processing sequence
is the thermal budget during FEOL and BEOL processes. FEOL processing involves
oxidation and etching of Si and hence it is often conducted at high temperatures (>400
◦ C). BEOL processes, which comprise placing dielectrics, metal interconnects, etc., are generally conducted at relatively low temperatures (<400
◦ C),
although dielectric deposition temperatures can sometimes reach 425–450
◦ C. Hence,
selecting the sequence in which TSVs should be fabricated is important, and has to
be often optimized on a case-by-case basis. For example, fabricating TSV assemblies
in the via-first sequence is the easiest of all process sequences, as it allows working
on a pristine Si wafer with no other structure. However, since there may be considerable difference between the CTE of the metal filler and Si, the FEOL processing
may lead to the build up of significant thermal stresses in the structure, resulting
in metal pumping, interfacial sliding, fracture, and other reliability issues. In addition, certain filler metals, for example Cu, are difficult to use in the via-first process
sequence due to their very fast diffusivity into Si at high temperatures. This limits