58
P. Kumar et al.
maximum distance between the hill and trough is less than 50 nm. Furthermore, it has
been reported that adding postetch wet-etching process using KOH and isopropyl
alcohol can reduce the surface roughness to 6 nm [37]. It has also been reported
that adding new steps in the above time multiplex alternate process by including
flow of either oxygen plasma or oxygen and argon plasmas [38, 39] can also reduce
the surface roughness as well as increase the overall depth of the Si holes. Another
strategy for reducing surface roughness is to perform a single step anisotropic etching
at the beginning of the etching process, followed by the usual time multiplexing
alternating method [21]. This method stems from the observation that the roughness
of Si walls created by the Bosch process deceases with an increase in the depth of
the hole [21].
3.3.2 Sequential Filling of Si Via
Once a blind hole is etched in Si, it is conformally filled with different classes of
materials. Of all of the material filling processes, the two most critical criteria are: (1)
step coverage and (2) void-free filling. For ensuring step coverage, it is desired to have
some taper in the Si via [16, 17]. Often a taper of 2
◦ –5
◦ (i.e., TSV-sidewall inclination
of 85
◦ –88
◦ relative to the Si-surface) is optimum for conformal coating [16]. Below,
with help of Fig. 3.1b, we describe the filling processes in detail:
1. Dielectric Layer: A thin layer of low-dielectric, i.e., a dielectric with high breakdown voltage, is placed over the walls of the Si hole to establish electrical isolation
between the current-carrying TSV-filler and the rest of the die. The most common
dielectric materials are SiO 2 , silicon nitrides, silicon oxynitride, tetra-ethyl orthosilicate (TEOS), etc. Most of these dielectrics are deposited by plasma enhanced
chemical vapor deposition (PE-CVD) technique, whereas SiO 2 can also be grown
using dry etching process. It is important to maintain a low thermal budget during
this process, especially when the TSVs are prepared after fabricating transistors,
etc. Polymers are another class of dielectric materials, which can be coated at
low temperatures and are suitable for low power applications. A common polymer dielectric material is parylene or poly(p-xylene) [40]. Another advantage of
using a soft and compliant polymer dielectric layer is that during thermal cycling,
it can accommodate the differential thermal strains produced between Si and the
metal filler (e.g., Cu) during thermal excursions, and hence minimize stresses
produced in the TSV assembly [41]. As shown in Fig. 3.8a, one of the ways to
coat polymers on Si is by first etching an annular trench concentric to the final via
and then filling it by spin-on polymer, followed by curing of the polymer [41].
Following coating of the polymer in the Si annular trench, the solid Si inside the
trench is etched, resulting in a blind hole with walls coated with polymers (see
Fig. 3.8a). As shown in Fig. 3.8b, this method allows conformal coating of Si
walls with the dielectric layer without voids. The thicknesses of oxide-based and
polymer-based dielectrics are 50–200 nm and 1–5 µm, respectively [41].
P. Kumar et al.
maximum distance between the hill and trough is less than 50 nm. Furthermore, it has
been reported that adding postetch wet-etching process using KOH and isopropyl
alcohol can reduce the surface roughness to 6 nm [37]. It has also been reported
that adding new steps in the above time multiplex alternate process by including
flow of either oxygen plasma or oxygen and argon plasmas [38, 39] can also reduce
the surface roughness as well as increase the overall depth of the Si holes. Another
strategy for reducing surface roughness is to perform a single step anisotropic etching
at the beginning of the etching process, followed by the usual time multiplexing
alternating method [21]. This method stems from the observation that the roughness
of Si walls created by the Bosch process deceases with an increase in the depth of
the hole [21].
3.3.2 Sequential Filling of Si Via
Once a blind hole is etched in Si, it is conformally filled with different classes of
materials. Of all of the material filling processes, the two most critical criteria are: (1)
step coverage and (2) void-free filling. For ensuring step coverage, it is desired to have
some taper in the Si via [16, 17]. Often a taper of 2
◦ –5
◦ (i.e., TSV-sidewall inclination
of 85
◦ –88
◦ relative to the Si-surface) is optimum for conformal coating [16]. Below,
with help of Fig. 3.1b, we describe the filling processes in detail:
1. Dielectric Layer: A thin layer of low-dielectric, i.e., a dielectric with high breakdown voltage, is placed over the walls of the Si hole to establish electrical isolation
between the current-carrying TSV-filler and the rest of the die. The most common
dielectric materials are SiO 2 , silicon nitrides, silicon oxynitride, tetra-ethyl orthosilicate (TEOS), etc. Most of these dielectrics are deposited by plasma enhanced
chemical vapor deposition (PE-CVD) technique, whereas SiO 2 can also be grown
using dry etching process. It is important to maintain a low thermal budget during
this process, especially when the TSVs are prepared after fabricating transistors,
etc. Polymers are another class of dielectric materials, which can be coated at
low temperatures and are suitable for low power applications. A common polymer dielectric material is parylene or poly(p-xylene) [40]. Another advantage of
using a soft and compliant polymer dielectric layer is that during thermal cycling,
it can accommodate the differential thermal strains produced between Si and the
metal filler (e.g., Cu) during thermal excursions, and hence minimize stresses
produced in the TSV assembly [41]. As shown in Fig. 3.8a, one of the ways to
coat polymers on Si is by first etching an annular trench concentric to the final via
and then filling it by spin-on polymer, followed by curing of the polymer [41].
Following coating of the polymer in the Si annular trench, the solid Si inside the
trench is etched, resulting in a blind hole with walls coated with polymers (see
Fig. 3.8a). As shown in Fig. 3.8b, this method allows conformal coating of Si
walls with the dielectric layer without voids. The thicknesses of oxide-based and
polymer-based dielectrics are 50–200 nm and 1–5 µm, respectively [41].