3 Materials and Processing of TSV
49
2. In case of a Via-last approach, the TSV may be realised starting from the wafer
frontside or from the wafer backside. Starting from the frontside of the wafer
requires etching through the back end of line (BEOL) stack.
3. Removal of the carrier-wafer before or after bonding (i.e., temporary bonding and
permanent bonding).
Table 3.1 provides an overview of the TSV materials and associated processes.
3.3 Fabrication of TSV and TSV Assembly
Fabrication of a TSV structure (or TSV assembly), comprises four main steps: (1)
etching of Si, where a hole or via in Si wafer is created, (2) filling, where the via
created in the previous step is sequentially filled with a dielectric layer, a diffusion
barrier and/or adhesion layer, a seed layer and a filler material, (3) planarization
and thinning of the structure after the filling step, followed by (4) deposition of
a redistribution layer with embedded circuitry to re-route electrical signals to the
chip stacked on top. Steps (1) through (3) are schematically illustrated in Fig. 3.1.
Most of the processes utilized during these three steps were originally developed for
fabrication of micro-electro-mechanical systems (MEMS) and integrated circuits
(ICs). Hence, these processes and the corresponding technologies are not strictly
new; however, these processes, as it will be explained below, have been significantly
modified and tailored for catering to the requirements of creating TSV structures.
The most unique feature of a TSV is that it is a high aspect ratio (HAR) structure
having very small cross-sectional area. Thus, the unique challenges associated with
fabricating TSV and TSV-assembly stem primarily from drilling a high aspect ratio
hole in Si wafer and then sequentially conformally filling it with a myriad of materials
belonging to different classes (e.g. metal, ceramics, etc.). Below, we describe the main
steps of fabricating a TSV assembly, and also highlight associated challenges and a
few methods of overcoming them.
3.3.1 Creating a Via or Trench in Si Wafer
A TSV usually has a diameter and a height in the range of 1–10 µm and 10–150 µm,
respectively [13–15]. Hence, the aspect ratios of TSVs are often in the range of
1–50. Generally, TSVs with small diameters are preferred for increasing the layout
efficiencies
1 and minimizing keep-out zone (KOZ).
2 In addition, the inner walls
of the holes should be slightly tapered (85–88
◦ [16]) and smooth for conformal
and void-free material filling [16–18]. The smooth wall of TSV also reduces stress
1 Layout efficiency is understood as the number of conductors per unit area.
2 KOZ is the region where functional properties of Si are significantly affected by the stress field of
the TSV.
49
2. In case of a Via-last approach, the TSV may be realised starting from the wafer
frontside or from the wafer backside. Starting from the frontside of the wafer
requires etching through the back end of line (BEOL) stack.
3. Removal of the carrier-wafer before or after bonding (i.e., temporary bonding and
permanent bonding).
Table 3.1 provides an overview of the TSV materials and associated processes.
3.3 Fabrication of TSV and TSV Assembly
Fabrication of a TSV structure (or TSV assembly), comprises four main steps: (1)
etching of Si, where a hole or via in Si wafer is created, (2) filling, where the via
created in the previous step is sequentially filled with a dielectric layer, a diffusion
barrier and/or adhesion layer, a seed layer and a filler material, (3) planarization
and thinning of the structure after the filling step, followed by (4) deposition of
a redistribution layer with embedded circuitry to re-route electrical signals to the
chip stacked on top. Steps (1) through (3) are schematically illustrated in Fig. 3.1.
Most of the processes utilized during these three steps were originally developed for
fabrication of micro-electro-mechanical systems (MEMS) and integrated circuits
(ICs). Hence, these processes and the corresponding technologies are not strictly
new; however, these processes, as it will be explained below, have been significantly
modified and tailored for catering to the requirements of creating TSV structures.
The most unique feature of a TSV is that it is a high aspect ratio (HAR) structure
having very small cross-sectional area. Thus, the unique challenges associated with
fabricating TSV and TSV-assembly stem primarily from drilling a high aspect ratio
hole in Si wafer and then sequentially conformally filling it with a myriad of materials
belonging to different classes (e.g. metal, ceramics, etc.). Below, we describe the main
steps of fabricating a TSV assembly, and also highlight associated challenges and a
few methods of overcoming them.
3.3.1 Creating a Via or Trench in Si Wafer
A TSV usually has a diameter and a height in the range of 1–10 µm and 10–150 µm,
respectively [13–15]. Hence, the aspect ratios of TSVs are often in the range of
1–50. Generally, TSVs with small diameters are preferred for increasing the layout
efficiencies
1 and minimizing keep-out zone (KOZ).
2 In addition, the inner walls
of the holes should be slightly tapered (85–88
◦ [16]) and smooth for conformal
and void-free material filling [16–18]. The smooth wall of TSV also reduces stress
1 Layout efficiency is understood as the number of conductors per unit area.
2 KOZ is the region where functional properties of Si are significantly affected by the stress field of
the TSV.