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P. Kumar et al.
thinned silicon dies. This circumvents the need for horizontal integration and reduces
communication bus-lengths, thereby improving performance while simultaneously
reducing the energy footprint of the package.
In this chapter, we focus on the materials and critical steps associated with fabricating TSVs and the flow process to fabricate TSV-enabled 3-D integration of silicon
dies. In the following chapter, we will introduce the microstructural and reliability
issues of TSVs.
3.2 Overview of TSV Materials and Processes
A TSV is composed of a conductor, passing through the Si substrate of the stacked
dies. The conductor is electrically insulated from the substrate by a dielectric layer,
i.e., the TSV liner, and interconnects the metal wires of the stacked dies. The TSV
liner also determines the TSV parasitic capacitance. In order to avoid diffusion of
metal from the TSV into the Si substrate, a barrier layer is used between the liner and
the TSV metal [1, 2]. The geometry of the TSV conductor may vary depending on the
3-D stacking technology. The area crossed by current may have different shapes, e.g.
square, rectangular, circular, elliptical and polygonal [3, 4]. In addition, the lateral
surface of the conductor can be cylindrical or conical [2].
The 3-D interconnection technology based on TSVs basically consists of three
main process modules: (1) The TSV module itself, (2) wafer thinning and backside
processing, and (3) the die or wafer stacking process (permanent bonding and/or
temporary bonding) [1]. The sequence of these process modules may vary and different process flows may be characterized by the following four key differentiating
characteristics [1]:
1. The order of the TSV process with respect to the device wafer fabrication process.
So we have Via-first, Via-middle and Via-last processes, c.f. Sect. 3.4.1.
2. The order of the TSV processing and 3D bonding.
3. The order of wafer thinning and 3D bonding.
4. The method of 3D bonding. We have Wafer-to-wafer (W2W) bonding, Die-towafer (D2W) bonding, and Die-to-die (D2D) bonding.
In addition to these four main characteristics, three secondary characteristics are
identified [1]:
1. Face-to-face (F2F) or back-to-face (B2F) bonding (the face or top surface of the
wafer being the side with the active devices and back-end interconnect layers),
c.f. Sect. 3.4.2.
P. Kumar et al.
thinned silicon dies. This circumvents the need for horizontal integration and reduces
communication bus-lengths, thereby improving performance while simultaneously
reducing the energy footprint of the package.
In this chapter, we focus on the materials and critical steps associated with fabricating TSVs and the flow process to fabricate TSV-enabled 3-D integration of silicon
dies. In the following chapter, we will introduce the microstructural and reliability
issues of TSVs.
3.2 Overview of TSV Materials and Processes
A TSV is composed of a conductor, passing through the Si substrate of the stacked
dies. The conductor is electrically insulated from the substrate by a dielectric layer,
i.e., the TSV liner, and interconnects the metal wires of the stacked dies. The TSV
liner also determines the TSV parasitic capacitance. In order to avoid diffusion of
metal from the TSV into the Si substrate, a barrier layer is used between the liner and
the TSV metal [1, 2]. The geometry of the TSV conductor may vary depending on the
3-D stacking technology. The area crossed by current may have different shapes, e.g.
square, rectangular, circular, elliptical and polygonal [3, 4]. In addition, the lateral
surface of the conductor can be cylindrical or conical [2].
The 3-D interconnection technology based on TSVs basically consists of three
main process modules: (1) The TSV module itself, (2) wafer thinning and backside
processing, and (3) the die or wafer stacking process (permanent bonding and/or
temporary bonding) [1]. The sequence of these process modules may vary and different process flows may be characterized by the following four key differentiating
characteristics [1]:
1. The order of the TSV process with respect to the device wafer fabrication process.
So we have Via-first, Via-middle and Via-last processes, c.f. Sect. 3.4.1.
2. The order of the TSV processing and 3D bonding.
3. The order of wafer thinning and 3D bonding.
4. The method of 3D bonding. We have Wafer-to-wafer (W2W) bonding, Die-towafer (D2W) bonding, and Die-to-die (D2D) bonding.
In addition to these four main characteristics, three secondary characteristics are
identified [1]:
1. Face-to-face (F2F) or back-to-face (B2F) bonding (the face or top surface of the
wafer being the side with the active devices and back-end interconnect layers),
c.f. Sect. 3.4.2.