Chapter 3
Materials and Processing of TSV
Praveen Kumar, Indranath Dutta, Zhiheng Huang, and Paul Conway
3.1 Introduction
With the evolution of electronics towards increasingly energy-efficient, mobile and
higher performance platforms, the requirements for packages with smaller formfactor, lighter weight and lower power, along with higher bandwidth and memory
capacity, has been accelerating. This has led to increasing use of 3-dimensional (3-D)
packaging of microelectronic devices, which can result in substantial reduction of
energy consumption per bit of information processed, due to a dramatic reduction
of package parasitics. Of the different types of stacked-die packages, area-array dies
interconnected with through-silicon vias (TSVs) has emerged as probably the best
3D-package architecture. In a typical 3-D package, multiple chips, each performing
a well-defined and independent task, are stacked in a vertical column. The vertically
stacked chips are then connected through solder micro-bumps, and communicate
with each other through metal-filled through-silicon vias, which are fabricated in the
P. Kumar
Department of Materials Engineering, Indian Institute of Science, Bangalore 560012, India
e-mail: praveenk@materials.iisc.ernet.in
I. Dutta (B)
School of Mechanical and Materials Engineering,
Washington State University, Pullma, WA 99164, USA
e-mail: idutta@wsu.edu
Z. Huang
School of Materials Science and Engineering,
Sun Yat-sen University, 135 West Xingang Road, Guangzhou 510275, China
e-mail: hzh29@mail.sysu.edu.cn
P. Conway
Electrical and Manufacturing Engineering, The Wolfson School of Mechanical,
Loughborough University, Loughborough, Leicestershire LE11 3TU, UK
e-mail: p.p.conway@lboro.ac.uk
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_3
47
Materials and Processing of TSV
Praveen Kumar, Indranath Dutta, Zhiheng Huang, and Paul Conway
3.1 Introduction
With the evolution of electronics towards increasingly energy-efficient, mobile and
higher performance platforms, the requirements for packages with smaller formfactor, lighter weight and lower power, along with higher bandwidth and memory
capacity, has been accelerating. This has led to increasing use of 3-dimensional (3-D)
packaging of microelectronic devices, which can result in substantial reduction of
energy consumption per bit of information processed, due to a dramatic reduction
of package parasitics. Of the different types of stacked-die packages, area-array dies
interconnected with through-silicon vias (TSVs) has emerged as probably the best
3D-package architecture. In a typical 3-D package, multiple chips, each performing
a well-defined and independent task, are stacked in a vertical column. The vertically
stacked chips are then connected through solder micro-bumps, and communicate
with each other through metal-filled through-silicon vias, which are fabricated in the
P. Kumar
Department of Materials Engineering, Indian Institute of Science, Bangalore 560012, India
e-mail: praveenk@materials.iisc.ernet.in
I. Dutta (B)
School of Mechanical and Materials Engineering,
Washington State University, Pullma, WA 99164, USA
e-mail: idutta@wsu.edu
Z. Huang
School of Materials Science and Engineering,
Sun Yat-sen University, 135 West Xingang Road, Guangzhou 510275, China
e-mail: hzh29@mail.sysu.edu.cn
P. Conway
Electrical and Manufacturing Engineering, The Wolfson School of Mechanical,
Loughborough University, Loughborough, Leicestershire LE11 3TU, UK
e-mail: p.p.conway@lboro.ac.uk
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_3
47