2 3D Packaging Architectures and Assembly Process Design
45
72. K. Sakuma, P.S. Andy, C.K. Tsang, S.L. Wright, B. Dang, C.S. Patel, B.C. Webb, J. Maria,
E.J. Sprogis, S.K. Kang, R.J. Polastre, R.R. Horton, J.U. Knockerbocker, 3D chip-stacking
technology with through-silicon vias and low-volume lead-free interconnections. IBM J. Res.
Dev. 52(6), 611–622 (2008)
73. http://ewh.ieee.org/soc/cpmt/presentations/cpmt1801.pdf