44
R. Mahajan and B. Sankman
57. T.M. Bauer, S.L. Shinde, J.E. Massad, D.L. Hetherington, Front end of line integration of
high density, electrically isolated, metallized through silicon vias, in Proceedings of the 58th
Electronic Components and Technology Conference (ECTC), May 2009, pp. 1165–1169
58. M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, Fabrication of 3D
packaging TSV using DRIE, design, test, integration and packaging of MEMS/MOEMS, 2008,
in Symposium on MEMS/MOEMS 2008, pp. 109–114. http://doi.org/10.1109/DTIP.2008.475
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59. G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J.F. Lugand, R. Anciant, N. Sillon,
Through silicon via technology using tungsten metallization, in 2011 IEEE International
Conference on IC Design & Technology (2011), pp. 1–4. https://doi.org/10.1109/icicdt.2011.
5783204
60. R. Agarwal, D. Hiner, S. Kannan, K. Lee, D. Kim, J. Paek, S. Kang, Y. Song, S. Dej, D. Smith,
S. Thangaraju, J. Paul, TSV integration on 20 nm logic: 3D assembly and reliability results,
in Proceedings of the 64th Electronic Components and Technology Conference (ECTC), May
2014, pp. 590–595
61. D.J. Na, K.O. Aung, W.K. Choi, T. Kida, T. Ochiai, T. Hashimoto, M. Kimura, K. Kata, S.W.
Yoon, A.C.B. Yong, TSV MEOL (mid end of line) and packaging technology of mobile 3DIC stacking, in Proceedings of the 64th Electronic *Components and Technology Conference
(ECTC), May 2014, pp. 596–600
62. N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N, Rajagopalan, B. Eaton, R. Mishra,
R. Yalamanchili, Z. Wang, S, Xia, K, Sapre, J, Hua, A. Chan, G. Mori, B. Linke, Robust TSV viamiddle and via-reveal process integration accomplished through characterization and management of sources of variation, in 2012 IEEE 62nd Electronic Components and Technology
Conference, pp, 787–793. https://doi.org/10.1109/ectc.2012.6248922
63. E. Beyne, Reliable via-middle copper through-silicon via technology for 3-D integration. IEEE
Trans. Compon. Pack. Manuf. Technol. 6(7), 983–992 (2016). https://doi.org/10.1109/tcpmt.
2015.2495166
64. S.W. Yoon, D.J. Na, K.T. Kang, W.K. Choi, C.B. Yong, Y.C. Kim, P.C. Marimuthu, TSV
MEOL (mid-end-of-line) and its assembly/packaging technology for 3D/2.5D solutions, in
ICEP-IAAC 2012 Proceedings, pp. 1–5
65. K.-W. Lee, H. Hashimoto, M. Onishi, Y. Sato, M. Murugesan, J.-C. Bea, T. Fukushima, T.
Tananka, M. Koyanagi, A resilient 3D stacked multicore processor fabricated using die-level 3D
integration and backside TSV technologies, in Proceedings of the 64th Electronic Components
and Technology Conference (ECTC), May 2014 pp. 304–308
66. M.-J. Tsai, Overview of ITRI’s TSV technology, in 7th Annual SEMATECH Symposium Japan, June 2011. http://www.sematech.org/meetings/archives/symposia/9237/Session%
205%203D%20interconnect/1%20MJ_Tsai_ITRI.pdf
67. H. Ikeda, Heterogeneous 3D stacking technology developments in ASET, in CPMT Symposium
Japan, 2012 2nd IEEE, pp. 1–4. https://doi.org/10.1109/icsj.2012.6523453
68. P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam, 3D interconnect through aligned wafer
level bonding, in Proceedings of the 52nd Electronic Components and Technology Conference
(ECTC), May 2002, pp. 1439–1443
69. T. Ohba, Wafer level three-dimensional integration (#DI) using bumpless TSV interconnects
for tera-scale generation, in 2013 IEEE, pp. 1–4
70. Q. Chen, D. Zhang, Z. Wang, L. Liu, J.J.-Q. Lu, Chip-to-wafer (C2W) 3D integration with wellcontrolled template alignment and wafer-level bonding, in Proceedings of the 61st Electronic
Components and Technology Conference (ECTC), May 2011, pp. 1–6
71. W.K. Choi, C.S. Premchandran, L. Xie, S.C. Ong, J.H. He, G.J. Yap, A. Yu, A novel die to wafer
(D2W) collective bonding method for MEMs and electronics a heterogeneous 3D integration,
in Proceedings of the 60th Electronic Components and Technology Conference (ECTC), May
2010, pp. 829–833
R. Mahajan and B. Sankman
57. T.M. Bauer, S.L. Shinde, J.E. Massad, D.L. Hetherington, Front end of line integration of
high density, electrically isolated, metallized through silicon vias, in Proceedings of the 58th
Electronic Components and Technology Conference (ECTC), May 2009, pp. 1165–1169
58. M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, Fabrication of 3D
packaging TSV using DRIE, design, test, integration and packaging of MEMS/MOEMS, 2008,
in Symposium on MEMS/MOEMS 2008, pp. 109–114. http://doi.org/10.1109/DTIP.2008.475
2963
59. G. Pares, N. Bresson, S. Minoret, V. Lapras, P. Brianceau, J.F. Lugand, R. Anciant, N. Sillon,
Through silicon via technology using tungsten metallization, in 2011 IEEE International
Conference on IC Design & Technology (2011), pp. 1–4. https://doi.org/10.1109/icicdt.2011.
5783204
60. R. Agarwal, D. Hiner, S. Kannan, K. Lee, D. Kim, J. Paek, S. Kang, Y. Song, S. Dej, D. Smith,
S. Thangaraju, J. Paul, TSV integration on 20 nm logic: 3D assembly and reliability results,
in Proceedings of the 64th Electronic Components and Technology Conference (ECTC), May
2014, pp. 590–595
61. D.J. Na, K.O. Aung, W.K. Choi, T. Kida, T. Ochiai, T. Hashimoto, M. Kimura, K. Kata, S.W.
Yoon, A.C.B. Yong, TSV MEOL (mid end of line) and packaging technology of mobile 3DIC stacking, in Proceedings of the 64th Electronic *Components and Technology Conference
(ECTC), May 2014, pp. 596–600
62. N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N, Rajagopalan, B. Eaton, R. Mishra,
R. Yalamanchili, Z. Wang, S, Xia, K, Sapre, J, Hua, A. Chan, G. Mori, B. Linke, Robust TSV viamiddle and via-reveal process integration accomplished through characterization and management of sources of variation, in 2012 IEEE 62nd Electronic Components and Technology
Conference, pp, 787–793. https://doi.org/10.1109/ectc.2012.6248922
63. E. Beyne, Reliable via-middle copper through-silicon via technology for 3-D integration. IEEE
Trans. Compon. Pack. Manuf. Technol. 6(7), 983–992 (2016). https://doi.org/10.1109/tcpmt.
2015.2495166
64. S.W. Yoon, D.J. Na, K.T. Kang, W.K. Choi, C.B. Yong, Y.C. Kim, P.C. Marimuthu, TSV
MEOL (mid-end-of-line) and its assembly/packaging technology for 3D/2.5D solutions, in
ICEP-IAAC 2012 Proceedings, pp. 1–5
65. K.-W. Lee, H. Hashimoto, M. Onishi, Y. Sato, M. Murugesan, J.-C. Bea, T. Fukushima, T.
Tananka, M. Koyanagi, A resilient 3D stacked multicore processor fabricated using die-level 3D
integration and backside TSV technologies, in Proceedings of the 64th Electronic Components
and Technology Conference (ECTC), May 2014 pp. 304–308
66. M.-J. Tsai, Overview of ITRI’s TSV technology, in 7th Annual SEMATECH Symposium Japan, June 2011. http://www.sematech.org/meetings/archives/symposia/9237/Session%
205%203D%20interconnect/1%20MJ_Tsai_ITRI.pdf
67. H. Ikeda, Heterogeneous 3D stacking technology developments in ASET, in CPMT Symposium
Japan, 2012 2nd IEEE, pp. 1–4. https://doi.org/10.1109/icsj.2012.6523453
68. P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, R. Islam, 3D interconnect through aligned wafer
level bonding, in Proceedings of the 52nd Electronic Components and Technology Conference
(ECTC), May 2002, pp. 1439–1443
69. T. Ohba, Wafer level three-dimensional integration (#DI) using bumpless TSV interconnects
for tera-scale generation, in 2013 IEEE, pp. 1–4
70. Q. Chen, D. Zhang, Z. Wang, L. Liu, J.J.-Q. Lu, Chip-to-wafer (C2W) 3D integration with wellcontrolled template alignment and wafer-level bonding, in Proceedings of the 61st Electronic
Components and Technology Conference (ECTC), May 2011, pp. 1–6
71. W.K. Choi, C.S. Premchandran, L. Xie, S.C. Ong, J.H. He, G.J. Yap, A. Yu, A novel die to wafer
(D2W) collective bonding method for MEMs and electronics a heterogeneous 3D integration,
in Proceedings of the 60th Electronic Components and Technology Conference (ECTC), May
2010, pp. 829–833