2 3D Packaging Architectures and Assembly Process Design
43
38. V.C. Venezia. C. Shih, W.Z. Yang, B. Zhang, H. Rhodes, Stack chip technology: a new direction
for CMOS imagers, in Presented at the IISW Conference (2015)
39. R. Fontaine, The state-of-the-art of mainstream CMOS image sensors, in Presented at the IISW
Conference (2015)
40. D/3D TSV & Wafer-Level Stacking Technology & Market Updates 2019. Yole Développement
41. K. Chandrashekar, W. Weis, B. Akesson, N. When, K. Goossens, System and circuit level
power modeling of energy-efficient 3D-stacked wide I/O DRAMs, in Presented at the 2013
DATE Conference, pp. 236–241
42. M.A. Karim, P.D. Franzon, A. Kumar, Power comparison of 2D, 3D and 2.5D interconnect
solutions and power optimization of interposer interconnects, in ECTC 2013, pp. 860–866
43. https://www.jedec.org/standards-documents/docs/jesd229–2
44. M.H. Hajkazemi, M.K. Tavana, H. Homayoun, Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies
in embedded MPSoCs, in Paper presented at the 33rd IEEE International Conference on
Computer Design (2015), pp. 70–77
45. Y. Zhang, X. Zhang, M. Bakir, Benchmarking digital Die-to-Die channels, in 2.5-D and 3-D
heterogeneous integration platforms. IEEE Trans. Electron Dev. 65(12) (2018), 5460–5467
46. S. Panth, K. Samadi, Y. Du, S.K. Lim, High density integration of functional modules using
monolithic 3D-IC technology, in Proceedings IEEE Asia South Pacific Design Automation
Conference, January 2013, pp. 681–686
47. T. Srimani, G. Hills, C. Lau, M. Shulaker, Monolithic three-dimensional imaging system:
carbon nanotube computing circuitry integrated directly over silicon imager, in 2019 Symposium on VLSI Technology Digest of Technical Papers, pp. T24–T25
48. M. Saeidi, K. Samadi, A. Mittal, R. Mittal, Thermal implications of mobile 3D-ICs, in Presented
at the 2014 3D Systems Integration Conference (3DIC) in Kinsdale, pp. 1–7. https://doi.org/
10.1109/3dic.2014.7152160
49. M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, H. Itani, Future system-onsilicon LSI chips. IEEE Micro 18(4), 17–22 (1998)
50. A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas, S. Domae, D.
Perry, M. Choi, A. Redolifi, C. Okoro, Y. Yang, J. Van Olmen, S. Thangaraju, D. Sabuncuoglu
Tezcan, P. Soussan, J.H. Cho, A. Yakovlev, P. Marchal, Y. Travaly, E. Beyne, S. Biesemans, B.
Swinnen, Comprehensive Analysis of the impact of single and arrays of through silicon vias
induced stress on high-K/metal gate CMOS performance, in IEDM (2010), pp. 2.2.1–2.2.4
51. W. Guo, G. Van der Plas, A. Ivankovic, V. Cherman, G. Eneman, B. De Wachter, M. Togo, A.
Redolfi, S. Kubicek, Y. Civale, T. Chiarella, B. Vandevelde, K. Croes, I. De Wolf, I. Debusschere,
A. Mercha, A. Thean, G. Beyer, B. Swinnen, E. Beyne. Impact of through silicon via induced
mechanical stress on fully depleted bulk finFET technology, IEDM (2012), pp. 18.4.1–18.4.4
52. T. Kauerauf, A. Branka, K. Croes, A. Redolfi, Y. Civale, C. Torregiani, G. Groeseneken, E.
Beyne. Effect of TSV presence on FEOL yield and reliability (2013), pp. 5C.6.1–5C.6.4
53. M. Tanaka, M. Sekine, I. Sakai, Y. Kusuda, T. Nonaka, O. Ysuji, K. Kondo, TSV Processes.
Three Dimensional Integration of Semiconductors (2015), pp. 43–96. http://rd.springer.com/
chapter/10.1007/978-3-18675-7_3/fulltext.html
54. S. Spiesshoefer, L. Schaper, IC stacking technology using fine pitch, nanoscale through silicon
vias, in Proceedings of IEEE 53rd Electronic Components and Technology Conference (ECTC),
May 2003, pp. 631–633
55. S. Spiesshoefer, L. Schaper, S. Burkett, G. Vangara, Z. Rahman, P. Arunasalam, Z-Axis interconnects using fine pitch, nanoscale through-silicon vias: process development, in Proceedings of IEEE 54th Electronic Components and Technology Conference (ECTC), June 2004,
pp. 466–471
56. N. Ranganathan, K. Prasad, N. Balasubramanian, Z. Qiaoer, S.C. Hwee, High aspect ratio
through-wafer interconnect for three dimensional integrated circuits, in Proceedings of IEEE
55th Electronic Components and Technology Conference (ECTC), (2005), pp. 343–348
43
38. V.C. Venezia. C. Shih, W.Z. Yang, B. Zhang, H. Rhodes, Stack chip technology: a new direction
for CMOS imagers, in Presented at the IISW Conference (2015)
39. R. Fontaine, The state-of-the-art of mainstream CMOS image sensors, in Presented at the IISW
Conference (2015)
40. D/3D TSV & Wafer-Level Stacking Technology & Market Updates 2019. Yole Développement
41. K. Chandrashekar, W. Weis, B. Akesson, N. When, K. Goossens, System and circuit level
power modeling of energy-efficient 3D-stacked wide I/O DRAMs, in Presented at the 2013
DATE Conference, pp. 236–241
42. M.A. Karim, P.D. Franzon, A. Kumar, Power comparison of 2D, 3D and 2.5D interconnect
solutions and power optimization of interposer interconnects, in ECTC 2013, pp. 860–866
43. https://www.jedec.org/standards-documents/docs/jesd229–2
44. M.H. Hajkazemi, M.K. Tavana, H. Homayoun, Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies
in embedded MPSoCs, in Paper presented at the 33rd IEEE International Conference on
Computer Design (2015), pp. 70–77
45. Y. Zhang, X. Zhang, M. Bakir, Benchmarking digital Die-to-Die channels, in 2.5-D and 3-D
heterogeneous integration platforms. IEEE Trans. Electron Dev. 65(12) (2018), 5460–5467
46. S. Panth, K. Samadi, Y. Du, S.K. Lim, High density integration of functional modules using
monolithic 3D-IC technology, in Proceedings IEEE Asia South Pacific Design Automation
Conference, January 2013, pp. 681–686
47. T. Srimani, G. Hills, C. Lau, M. Shulaker, Monolithic three-dimensional imaging system:
carbon nanotube computing circuitry integrated directly over silicon imager, in 2019 Symposium on VLSI Technology Digest of Technical Papers, pp. T24–T25
48. M. Saeidi, K. Samadi, A. Mittal, R. Mittal, Thermal implications of mobile 3D-ICs, in Presented
at the 2014 3D Systems Integration Conference (3DIC) in Kinsdale, pp. 1–7. https://doi.org/
10.1109/3dic.2014.7152160
49. M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa, H. Itani, Future system-onsilicon LSI chips. IEEE Micro 18(4), 17–22 (1998)
50. A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas, S. Domae, D.
Perry, M. Choi, A. Redolifi, C. Okoro, Y. Yang, J. Van Olmen, S. Thangaraju, D. Sabuncuoglu
Tezcan, P. Soussan, J.H. Cho, A. Yakovlev, P. Marchal, Y. Travaly, E. Beyne, S. Biesemans, B.
Swinnen, Comprehensive Analysis of the impact of single and arrays of through silicon vias
induced stress on high-K/metal gate CMOS performance, in IEDM (2010), pp. 2.2.1–2.2.4
51. W. Guo, G. Van der Plas, A. Ivankovic, V. Cherman, G. Eneman, B. De Wachter, M. Togo, A.
Redolfi, S. Kubicek, Y. Civale, T. Chiarella, B. Vandevelde, K. Croes, I. De Wolf, I. Debusschere,
A. Mercha, A. Thean, G. Beyer, B. Swinnen, E. Beyne. Impact of through silicon via induced
mechanical stress on fully depleted bulk finFET technology, IEDM (2012), pp. 18.4.1–18.4.4
52. T. Kauerauf, A. Branka, K. Croes, A. Redolfi, Y. Civale, C. Torregiani, G. Groeseneken, E.
Beyne. Effect of TSV presence on FEOL yield and reliability (2013), pp. 5C.6.1–5C.6.4
53. M. Tanaka, M. Sekine, I. Sakai, Y. Kusuda, T. Nonaka, O. Ysuji, K. Kondo, TSV Processes.
Three Dimensional Integration of Semiconductors (2015), pp. 43–96. http://rd.springer.com/
chapter/10.1007/978-3-18675-7_3/fulltext.html
54. S. Spiesshoefer, L. Schaper, IC stacking technology using fine pitch, nanoscale through silicon
vias, in Proceedings of IEEE 53rd Electronic Components and Technology Conference (ECTC),
May 2003, pp. 631–633
55. S. Spiesshoefer, L. Schaper, S. Burkett, G. Vangara, Z. Rahman, P. Arunasalam, Z-Axis interconnects using fine pitch, nanoscale through-silicon vias: process development, in Proceedings of IEEE 54th Electronic Components and Technology Conference (ECTC), June 2004,
pp. 466–471
56. N. Ranganathan, K. Prasad, N. Balasubramanian, Z. Qiaoer, S.C. Hwee, High aspect ratio
through-wafer interconnect for three dimensional integrated circuits, in Proceedings of IEEE
55th Electronic Components and Technology Conference (ECTC), (2005), pp. 343–348