42
R. Mahajan and B. Sankman
21. F. Mukta, S.S. Iyer, 3D integration review. Sci. China Inf. Serv. 54(5), 1012–1025 (2011)
22. L. England, I. Arsovski, Advanced packaging saves the day!—How TSV technology will
enable continued scaling, IEDM 2017
23. A. Eitan, K.-Y. Hung, Thermo-compression bonding for fine-pitch copper-pillar flip-chip interconnect—tool features as enablers of unique technology, in Proceedings IEEE 65th Electronic
Components and Technology Conference (ECTC), May 2015 pp. 460–464
24. G. Vakanas, O. Minho, B. Dimcic, K. Vanstreels, B. Vandecasteele, I. De Preter, J.
Derakhshandeh, K. Rebibis, M. Kajihara, I. De Wolf, Formation, processing and characterization of Co-Sn intermetallic compounds for potential integration in 3D interconnects.
Microelectron. Eng. 140, 72–80 (2015)
25. A. Klumpp, R. Merkel, P. Ramm, J. Weber, R. Weiland, Vertical system integration by using
inter-chip vias and solid-liquid interdiffusion bonding. Jpn. J. Appl. Phys. 43(7A), L829–L830
(2004)
26. P.R. Morrow, C.-M. Park, S. Ramanathan, M.J. Kobrinsky, M. Harmes, Three-dimensional
wafer stacking via Cu–Cu bonding integrated with 65-nm strained Si/low-k CMOS technology.
IEEE Electron. Device Lett. 27(5) (2006)
27. P. Batra, S. Skordas, D. LaTulipe, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He,
D.W. Gamage, J. Golz, W. Lin, T. Vo, D. Priyadarshini, A. Hubbard, K. Cauffman, B. Peethala,
J. Barth, T. Kirihata, T. Graves-Abe, N. Robson, S. Iyer, Three-dimensonal wafer stacking using
Cu TSV integrated with 45 nm high performance SOI-CMOS embedded DRAM technology.
J. Low Power Electron. Appl. 4, 77–89 (2014). https://doi.org/10.3390/jlpea4020077
28. K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, M.
Bonkohara, Ultra-high-density interconnection technology of three-dimensional packaging.
Microelectron. Reliab. 43, 1267–1279 (2003)
29. C.S. Tan, G.Y. Chong, High throughput Cu–Cu bonding by non-thermo-compression method,
in Paper presented at the 63rd Electronic Components and Technology Conference, Las Vegas,
Nevada (2013), pp. 1158–1164
30. P. Guegen, C. Ventosa, L. Di Cioccio, H. Moriceau, F. Grossi, M. Rivoire, P. Leduc, L. Clavelier, Physics of direct bonding: applications to 3D heterogeneous or monolithic integration,
Microelectron. Eng. 87, 477–484 (2010)
31. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G.H. Loh, D. McCauley,
P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb,
Die stacking (3D) microarchitecture, in Paper presented at the 39th Annual IEEE/ACM
International Symposium on Microarchitecture (MICRO’06) (2006)
32. J.M. Stern, V.H. Ozguz, 3D system architectures, in Intelligent Integrated Microsystems, ed. by
R.A. Athale, J. C. Wolper, Proc. SPIE 6232, 6232K (2006). https://doi.org/10.1117/12.667381
33. P. Jacob, O. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft, J.F. McDonald, Predicting the
performance of a 3D processor-memory chip stack. IEEE Des. Test Comput. 540–547 (2005)
34. P. Franzon, E. Rotenberg, J. Tuck, W.R. Davis, H. Zhou, J. Schabel, Z. Zhang, J.B. Dwiel, E.
Forbes, J. Huh, S. Lipa, Computing in 3D, in Presented at the 2015 Custom Integrated Circuits
Conference (CICC), 2015, 28–30 Sept 2015, pp. 1–6
35. U. Kang, H.-J. Chnug, S. Heo, D.-H. Park, H. Lee, J.H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn,
D. Kwan, J.-W. Lee, H.-S. Joo, W.-S. Kim, D.H. Jang, N.S. Kim, J.-H. Choi, T.-G. Chung,
J.-H. Yoo, J.S. Choi, C. Kim, Y.-H. Jun, 8 Gb 3-D DDR3 DRAM using through-silicon-via
technology. IEEE J. Solid-State Circ. 45(1), 111–119 (2010)
36. J.B. Park, W.R. Davis, P.D. Franzon, 3-D-DATE: a circuit-level three-dimensional DRAM area,
timing, and energy model. IEEE Trans. Circ. Syst.-I, Reg. Pap. 66(2), 756–768 (2019)
37. S. Lhostis, A. Farcy, E. Deloffre, F. Lorut, S. Mermoz, Y. Henrion, L. Bethier, F. Bailly, D,
Scevola, F. Gyuader, F. Gigon, C. Besset, S. Pellssier, L. Gay, N. Hetellier, M. Arnoux, A.-L.
Le Berrigo, S. Moreau, V. Balan, F. Fournel, A. Jouce, S. Cheramy, B. Rebhan, G. Maier, L.
Chitu, Reliable 300 mm wafer level hybrid bonding for 3D stacked CMOS image sensors, in
Paper presented at the 66 th Electronic Components and Technology Conference, Las Vegas,
Nevada, June 2016, pp. 869–876
R. Mahajan and B. Sankman
21. F. Mukta, S.S. Iyer, 3D integration review. Sci. China Inf. Serv. 54(5), 1012–1025 (2011)
22. L. England, I. Arsovski, Advanced packaging saves the day!—How TSV technology will
enable continued scaling, IEDM 2017
23. A. Eitan, K.-Y. Hung, Thermo-compression bonding for fine-pitch copper-pillar flip-chip interconnect—tool features as enablers of unique technology, in Proceedings IEEE 65th Electronic
Components and Technology Conference (ECTC), May 2015 pp. 460–464
24. G. Vakanas, O. Minho, B. Dimcic, K. Vanstreels, B. Vandecasteele, I. De Preter, J.
Derakhshandeh, K. Rebibis, M. Kajihara, I. De Wolf, Formation, processing and characterization of Co-Sn intermetallic compounds for potential integration in 3D interconnects.
Microelectron. Eng. 140, 72–80 (2015)
25. A. Klumpp, R. Merkel, P. Ramm, J. Weber, R. Weiland, Vertical system integration by using
inter-chip vias and solid-liquid interdiffusion bonding. Jpn. J. Appl. Phys. 43(7A), L829–L830
(2004)
26. P.R. Morrow, C.-M. Park, S. Ramanathan, M.J. Kobrinsky, M. Harmes, Three-dimensional
wafer stacking via Cu–Cu bonding integrated with 65-nm strained Si/low-k CMOS technology.
IEEE Electron. Device Lett. 27(5) (2006)
27. P. Batra, S. Skordas, D. LaTulipe, K. Winstel, C. Kothandaraman, B. Himmel, G. Maier, B. He,
D.W. Gamage, J. Golz, W. Lin, T. Vo, D. Priyadarshini, A. Hubbard, K. Cauffman, B. Peethala,
J. Barth, T. Kirihata, T. Graves-Abe, N. Robson, S. Iyer, Three-dimensonal wafer stacking using
Cu TSV integrated with 45 nm high performance SOI-CMOS embedded DRAM technology.
J. Low Power Electron. Appl. 4, 77–89 (2014). https://doi.org/10.3390/jlpea4020077
28. K. Takahashi, M. Umemoto, N. Tanaka, K. Tanida, Y. Nemoto, Y. Tomita, M. Tago, M.
Bonkohara, Ultra-high-density interconnection technology of three-dimensional packaging.
Microelectron. Reliab. 43, 1267–1279 (2003)
29. C.S. Tan, G.Y. Chong, High throughput Cu–Cu bonding by non-thermo-compression method,
in Paper presented at the 63rd Electronic Components and Technology Conference, Las Vegas,
Nevada (2013), pp. 1158–1164
30. P. Guegen, C. Ventosa, L. Di Cioccio, H. Moriceau, F. Grossi, M. Rivoire, P. Leduc, L. Clavelier, Physics of direct bonding: applications to 3D heterogeneous or monolithic integration,
Microelectron. Eng. 87, 477–484 (2010)
31. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G.H. Loh, D. McCauley,
P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb,
Die stacking (3D) microarchitecture, in Paper presented at the 39th Annual IEEE/ACM
International Symposium on Microarchitecture (MICRO’06) (2006)
32. J.M. Stern, V.H. Ozguz, 3D system architectures, in Intelligent Integrated Microsystems, ed. by
R.A. Athale, J. C. Wolper, Proc. SPIE 6232, 6232K (2006). https://doi.org/10.1117/12.667381
33. P. Jacob, O. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft, J.F. McDonald, Predicting the
performance of a 3D processor-memory chip stack. IEEE Des. Test Comput. 540–547 (2005)
34. P. Franzon, E. Rotenberg, J. Tuck, W.R. Davis, H. Zhou, J. Schabel, Z. Zhang, J.B. Dwiel, E.
Forbes, J. Huh, S. Lipa, Computing in 3D, in Presented at the 2015 Custom Integrated Circuits
Conference (CICC), 2015, 28–30 Sept 2015, pp. 1–6
35. U. Kang, H.-J. Chnug, S. Heo, D.-H. Park, H. Lee, J.H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn,
D. Kwan, J.-W. Lee, H.-S. Joo, W.-S. Kim, D.H. Jang, N.S. Kim, J.-H. Choi, T.-G. Chung,
J.-H. Yoo, J.S. Choi, C. Kim, Y.-H. Jun, 8 Gb 3-D DDR3 DRAM using through-silicon-via
technology. IEEE J. Solid-State Circ. 45(1), 111–119 (2010)
36. J.B. Park, W.R. Davis, P.D. Franzon, 3-D-DATE: a circuit-level three-dimensional DRAM area,
timing, and energy model. IEEE Trans. Circ. Syst.-I, Reg. Pap. 66(2), 756–768 (2019)
37. S. Lhostis, A. Farcy, E. Deloffre, F. Lorut, S. Mermoz, Y. Henrion, L. Bethier, F. Bailly, D,
Scevola, F. Gyuader, F. Gigon, C. Besset, S. Pellssier, L. Gay, N. Hetellier, M. Arnoux, A.-L.
Le Berrigo, S. Moreau, V. Balan, F. Fournel, A. Jouce, S. Cheramy, B. Rebhan, G. Maier, L.
Chitu, Reliable 300 mm wafer level hybrid bonding for 3D stacked CMOS image sensors, in
Paper presented at the 66 th Electronic Components and Technology Conference, Las Vegas,
Nevada, June 2016, pp. 869–876