2 3D Packaging Architectures and Assembly Process Design
41
Corporation) on test processes is also gratefully acknowledged. The editors would like to thank
Zhiheng Huang from Sun Yat-sen University for his critical review of this chapter.
References
1. https://www.anandtech.com/tag/hbm2
2. https://newsroom.intel.com/wp-content/uploads/sites/11/2019/08/Intel-Lakefield-HotChipspresentation.pdf
3. D. Ingerly, S. Amin, L. Aryasomayajula, A. Balankutty, D. Borst, A. Chandra, K. Cheemalapati,
C.S. Cook, R. Criss, K. Enamul, W. Gomes, D. Jones, K.C. Kolluri, A. Kandas, G.-S. Kim,
H. Ma, D. Pantuso, C.F. Petersburg, M. Phen-Givoni, A.M. Pallai, A. Sairam, P. Shekhar, P.
Sinha. P. Stover, A. Telang, Z. Zell, Foveros: 3D integration and the use of face to face stacking
for logic devices, in IEDM 2019
4. A.A. Elsherbini, S.M. Liff, J.M. Swan, Heterogeneous integration using omni-directional
interconnect packaging, in IEDM 2019
5. G. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114 (1965)
6. R. Thakur, 50 Years of Moore’s law. Solid State Technol. 58(4), 41 (2015)
7. https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html
8. R. Tummala, System On Package: Miniaturization of the Entire System (The McGraw-Hill
Companies Inc., 2008)
9. https://www.anandtech.com/show/6911/intels-return-to-the-dram-business-haswell-gt3e-tointegrate-128mb-edram
10. http://www.hybridmemorycube.org/
11. https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.html?
wapkw=agilex
12. R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama,
S. Sharan, D. Iyengar, D. Mallik, Embedded multi-die interconnect bridge (EMIB)—A high
density, high bandwidth packaging interconnect, in Paper presented at the 66th Electronic
Components and Technology Conference, Las Vegas, Nevada 557–565, June 2016
13. M. Sunohara, et al., Silicon interposer with TSVs (through silicon vias) and fine multilayer
wiring, in Proceedings of IEEE Electronic Components and Technology Conference (ECTC),
Lake Buena Vista, FL, May 27–30, 2008, pp. 847–852
14. K. Oi, et al., Development of new 2.5D package with novel integrated organic interposer
substrate with ultra-fine wiring and high density bumps, in Proceedings of the 2014 IEEE 64th
Electronic Components and Technology Conference, Orlando, pp. 348–353
15. S. Miki, H. Taneda, N. Kobayashi, K. Oi, K. Nagai, T. Koyama, Development of 2.3D high
density organic package using low temperature bonding process with Sn–Bi solder, in Proceedings of the 2019 IEEE 69th Electronic Components and Technology Conference, Las Vegas,
pp. 1599–1604
16. X. Zhang, P.K. Jo, M. Zia, G.S. May, M.S. Bakir, Heterogeneous interconnect stitching technology with compressible microinterconnects for dense multi-die integration. IEEE Electron
Device Lett. 38(2) (2017)
17. W.R. Davis, J. Wilson, J. Xu, L. Luo, H. Hua, A. Sule, C.A. Mineo, M.B. Steer, P.D. Franzon,
Demystifying 3D ICs: the pros and cons of going vertical, design and test of computers, IEEE
22(6), 498–510 (2005)
18. J.D. Meindl, Interconnect opportunities for gigascale integration. IEEE Micro 28–35 (2003)
19. J.D. Meindl, Beyond Moore’s law: the interconnect era. Comput. Sci. Eng. 20–24 (2003)
20. R.S. Patti, Three-dimensional integrated circuits and the future of system-on-chip designs.
Proc. IEEE 94(6), 1214–1224 (2006)
41
Corporation) on test processes is also gratefully acknowledged. The editors would like to thank
Zhiheng Huang from Sun Yat-sen University for his critical review of this chapter.
References
1. https://www.anandtech.com/tag/hbm2
2. https://newsroom.intel.com/wp-content/uploads/sites/11/2019/08/Intel-Lakefield-HotChipspresentation.pdf
3. D. Ingerly, S. Amin, L. Aryasomayajula, A. Balankutty, D. Borst, A. Chandra, K. Cheemalapati,
C.S. Cook, R. Criss, K. Enamul, W. Gomes, D. Jones, K.C. Kolluri, A. Kandas, G.-S. Kim,
H. Ma, D. Pantuso, C.F. Petersburg, M. Phen-Givoni, A.M. Pallai, A. Sairam, P. Shekhar, P.
Sinha. P. Stover, A. Telang, Z. Zell, Foveros: 3D integration and the use of face to face stacking
for logic devices, in IEDM 2019
4. A.A. Elsherbini, S.M. Liff, J.M. Swan, Heterogeneous integration using omni-directional
interconnect packaging, in IEDM 2019
5. G. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114 (1965)
6. R. Thakur, 50 Years of Moore’s law. Solid State Technol. 58(4), 41 (2015)
7. https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html
8. R. Tummala, System On Package: Miniaturization of the Entire System (The McGraw-Hill
Companies Inc., 2008)
9. https://www.anandtech.com/show/6911/intels-return-to-the-dram-business-haswell-gt3e-tointegrate-128mb-edram
10. http://www.hybridmemorycube.org/
11. https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.html?
wapkw=agilex
12. R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama,
S. Sharan, D. Iyengar, D. Mallik, Embedded multi-die interconnect bridge (EMIB)—A high
density, high bandwidth packaging interconnect, in Paper presented at the 66th Electronic
Components and Technology Conference, Las Vegas, Nevada 557–565, June 2016
13. M. Sunohara, et al., Silicon interposer with TSVs (through silicon vias) and fine multilayer
wiring, in Proceedings of IEEE Electronic Components and Technology Conference (ECTC),
Lake Buena Vista, FL, May 27–30, 2008, pp. 847–852
14. K. Oi, et al., Development of new 2.5D package with novel integrated organic interposer
substrate with ultra-fine wiring and high density bumps, in Proceedings of the 2014 IEEE 64th
Electronic Components and Technology Conference, Orlando, pp. 348–353
15. S. Miki, H. Taneda, N. Kobayashi, K. Oi, K. Nagai, T. Koyama, Development of 2.3D high
density organic package using low temperature bonding process with Sn–Bi solder, in Proceedings of the 2019 IEEE 69th Electronic Components and Technology Conference, Las Vegas,
pp. 1599–1604
16. X. Zhang, P.K. Jo, M. Zia, G.S. May, M.S. Bakir, Heterogeneous interconnect stitching technology with compressible microinterconnects for dense multi-die integration. IEEE Electron
Device Lett. 38(2) (2017)
17. W.R. Davis, J. Wilson, J. Xu, L. Luo, H. Hua, A. Sule, C.A. Mineo, M.B. Steer, P.D. Franzon,
Demystifying 3D ICs: the pros and cons of going vertical, design and test of computers, IEEE
22(6), 498–510 (2005)
18. J.D. Meindl, Interconnect opportunities for gigascale integration. IEEE Micro 28–35 (2003)
19. J.D. Meindl, Beyond Moore’s law: the interconnect era. Comput. Sci. Eng. 20–24 (2003)
20. R.S. Patti, Three-dimensional integrated circuits and the future of system-on-chip designs.
Proc. IEEE 94(6), 1214–1224 (2006)