40
R. Mahajan and B. Sankman
package. Additionally, since the heat path for Chip 1 is impeded by Chip 2, precise
temperature control of Chip 1 during full functional test is more challenging than in
the corresponding side-by-side case. Both of these constraints imply that there are
more challenges with stacked die testing versus side-by-side, and the potential for
higher compound yield loss is greater too.
2.6 Challenges with 3D TSV Architectures
It should be clear from the discussion so far that that TSV based architectures, while
attractive from a performance and power efficiency perspective, can limit product
performance from a thermal perspective. Increasing the thermal envelope of 3D
stacks is an important challenge. Considerable research in enhancing conduction
and convection modes of heat transfer are described in Chap. 13. 3D TSV stacks
break existing paradigms and require new design tools that accommodate the area
and stress impacts on transistor performance while taking advantage of the newly
available vertical TSV interconnects.
From a manufacturing perspective, TSV manufacturing processes create greater
overlap between backend silicon fabrication and assembly technologies. Additionally, it requires considerable investment in new equipment such as deep via etchers,
high aspect ratio Cu plating, ultra-thin wafer handling, and stacked die assembly.
Stacked die assembly drives the need for new materials such as fluxes that work
in narrow chip gaps with minimal residue, and high thermal conductivity underfills
that are compatible with different assembly flows, as well as incorporation of novel
Cu–Cu bonding technologies. 3D stacks drive new Test paradigms including fine
pitch test and a very detailed understanding of KGD and KGSD.
2.7 Summary
TSV based 3D stacking has generated considerable interest in the past two decades
and the considerable research and development effort in architecture and manufacturing has resulted in a detailed understanding of multiple aspects of the technology.
In this chapter a broad overview of the value and importance of SIP packages has
been provided along with motivation for TSV based 3D architectures.
Acknowledgements The authors would like to acknowledge Prismark Partners LLC, TechSearch
International Inc, and Yole Développement for their generous permission to use their pictures.
Thanks are due to Dr. Zhiguo Qian (Intel Corporation) for his help on the section on IO power dissipation, Dr. Chandra Mohan Jha (Intel Corporation) for help with thermal analysis, Professor Paul
Franzon (North Carolina State University) for help getting updated latency and energy comparisons
Debendra Mallik for help on the figures, Sriram Srinivasan for thorough review of the chapter and
Tom DeBonis for his help in facilitating information collection. Guidance from Chris Nelson (Intel
R. Mahajan and B. Sankman
package. Additionally, since the heat path for Chip 1 is impeded by Chip 2, precise
temperature control of Chip 1 during full functional test is more challenging than in
the corresponding side-by-side case. Both of these constraints imply that there are
more challenges with stacked die testing versus side-by-side, and the potential for
higher compound yield loss is greater too.
2.6 Challenges with 3D TSV Architectures
It should be clear from the discussion so far that that TSV based architectures, while
attractive from a performance and power efficiency perspective, can limit product
performance from a thermal perspective. Increasing the thermal envelope of 3D
stacks is an important challenge. Considerable research in enhancing conduction
and convection modes of heat transfer are described in Chap. 13. 3D TSV stacks
break existing paradigms and require new design tools that accommodate the area
and stress impacts on transistor performance while taking advantage of the newly
available vertical TSV interconnects.
From a manufacturing perspective, TSV manufacturing processes create greater
overlap between backend silicon fabrication and assembly technologies. Additionally, it requires considerable investment in new equipment such as deep via etchers,
high aspect ratio Cu plating, ultra-thin wafer handling, and stacked die assembly.
Stacked die assembly drives the need for new materials such as fluxes that work
in narrow chip gaps with minimal residue, and high thermal conductivity underfills
that are compatible with different assembly flows, as well as incorporation of novel
Cu–Cu bonding technologies. 3D stacks drive new Test paradigms including fine
pitch test and a very detailed understanding of KGD and KGSD.
2.7 Summary
TSV based 3D stacking has generated considerable interest in the past two decades
and the considerable research and development effort in architecture and manufacturing has resulted in a detailed understanding of multiple aspects of the technology.
In this chapter a broad overview of the value and importance of SIP packages has
been provided along with motivation for TSV based 3D architectures.
Acknowledgements The authors would like to acknowledge Prismark Partners LLC, TechSearch
International Inc, and Yole Développement for their generous permission to use their pictures.
Thanks are due to Dr. Zhiguo Qian (Intel Corporation) for his help on the section on IO power dissipation, Dr. Chandra Mohan Jha (Intel Corporation) for help with thermal analysis, Professor Paul
Franzon (North Carolina State University) for help getting updated latency and energy comparisons
Debendra Mallik for help on the figures, Sriram Srinivasan for thorough review of the chapter and
Tom DeBonis for his help in facilitating information collection. Guidance from Chris Nelson (Intel