Chapter 18
Fault Isolation and Failure Analysis
of 3D Packaging
Yan Li and Deepak Goyal
18.1 Introduction
3D microelectronic packaging is the industry trend to meet the ever increasing market
demand for increased performance, lower power, smaller footprint, lower cost and
integration of heterogeneous devices. Chapters 1 and 2 have discussed in detail the
various types of 3D packages, having die to die 3D integration, package to package
3D integration, or heterogeneous 3D integration combining both package and die
stacking.
Figure 18.1 illustrates the schematic of a System in a Package (SIP), a 3D package
with a Package on Package (POP) configuration, where a field-programmable gate
array (FPGA), in the form of a ball grid array (BGA) package, is mounted in tandem
with a flip chip CPU die onto a common package substrate [1]. The resultant joint
between the FPGA package and the substrate is termed mid-level interconnect (MLI).
While the solder joints connecting the CPU to the substrate or the FPGA die to FPGA
substrate are called first level interconnects (FLI). With multiple levels of solder interconnects, Si dice and packages integrated into one SIP package, numerous failures,
for example solder joint non wet or cracks in FLI or MLI, substrate trace cracks in
either FPGA substrates or SIP substrates, delamination in either the CPU or the FPGA
die could happen in a single SIP package post reliability tests. Isolating the locations
of each failure and accessing the failing features or interconnects for physical failure
analysis in such complex package architectures is a significant challenge.
Figure 18.2 shows the schematic of a 3D package with stacked dice and TSV
Y. Li (B) · D. Goyal
Intel Corporation, Chandler, AZ, USA
e-mail: yan.a.li@intel.com
D. Goyal
e-mail: deepak.goyal@intel.com
© This is a U.S. government work and not under copyright protection in the U.S.;
foreign copyright protection may apply 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_18
575
Fault Isolation and Failure Analysis
of 3D Packaging
Yan Li and Deepak Goyal
18.1 Introduction
3D microelectronic packaging is the industry trend to meet the ever increasing market
demand for increased performance, lower power, smaller footprint, lower cost and
integration of heterogeneous devices. Chapters 1 and 2 have discussed in detail the
various types of 3D packages, having die to die 3D integration, package to package
3D integration, or heterogeneous 3D integration combining both package and die
stacking.
Figure 18.1 illustrates the schematic of a System in a Package (SIP), a 3D package
with a Package on Package (POP) configuration, where a field-programmable gate
array (FPGA), in the form of a ball grid array (BGA) package, is mounted in tandem
with a flip chip CPU die onto a common package substrate [1]. The resultant joint
between the FPGA package and the substrate is termed mid-level interconnect (MLI).
While the solder joints connecting the CPU to the substrate or the FPGA die to FPGA
substrate are called first level interconnects (FLI). With multiple levels of solder interconnects, Si dice and packages integrated into one SIP package, numerous failures,
for example solder joint non wet or cracks in FLI or MLI, substrate trace cracks in
either FPGA substrates or SIP substrates, delamination in either the CPU or the FPGA
die could happen in a single SIP package post reliability tests. Isolating the locations
of each failure and accessing the failing features or interconnects for physical failure
analysis in such complex package architectures is a significant challenge.
Figure 18.2 shows the schematic of a 3D package with stacked dice and TSV
Y. Li (B) · D. Goyal
Intel Corporation, Chandler, AZ, USA
e-mail: yan.a.li@intel.com
D. Goyal
e-mail: deepak.goyal@intel.com
© This is a U.S. government work and not under copyright protection in the U.S.;
foreign copyright protection may apply 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_18
575