17 Interconnect Quality and Reliability of 3D Packaging
555
F(t) = 1 − exp
−
t
η
β
(17.1)
where F(t) is percentage or fraction of the failed sample as a function of time, η is
the characteristic lifetime, and β is the shape factor or the slope of the Weibull plot.
In Black’s MTTF equation, there are three parameters: pre-factor A, current density
power factor n, and activation energy E a :
MTTF = A
j
−n
exp
E a
kT
(17.2)
With Black’s equation, we can determine those parameters experimentally and
obtain the statistical analysis. We need to conduct at the least the EM tests at two
temperatures and two current densities. To find the activation energy and to determine
n, we will not repeat them here, and the reader can use Google search or textbooks.
17.5.2 Experimental Studies of Electromigration in al
and Cu Interconnects
In the Al(Cu) interconnect, W via plugs are used to make vertical connections
between different layers of Al lines, for example, the M2 or M1 metallization layers
as shown in Fig. 17.29a. Since the atomic diffusion of W is much slower than Al,
there will be flux divergence of Al atoms as well as vacancies located over the top
of W via, and the divergence leads to hillock and void formation [37–40].
In comparison, the Cu dual-damascene structure is differently constructed [41,
42]. In Cu dual-damascene interconnects, the lower-level M2 trench and V1 that
connects to the M1 level are simultaneously prepared before Cu electroplating, as
shown in Fig. 17.29b. The M1 level is also separated from the V1 via by an electrically
conducting diffusion barrier (DB) that also coats the inner walls of V1 and the side
and bottom walls of the M2 trench. Consequently, the dual-damascene process places
the flux divergence, not at the V1/M2 interface, which is the top of V1 as in Al(Cu),
but at the M1/V1 interface at the bottom of V1. This via-bottom flux divergence is
potentially problematic from a reliability standpoint because only a small amount of
material depletion by EM will be sufficient for voiding damage to occur.
The dual-damascene interconnect is distinctly different from the previous Al(Cu)
architecture in another respect. It has been shown that EM in Cu interconnect occurs
by surface diffusion at the device operation temperature of 100 °C. In processing the
dual-damascene architecture, the top surface after electroplating must be chemicalmechanically polished and capped by a nitride layer before building of the next layer
[43]. Because of the weak chemical bonding between the nitride and Cu, the interface
can be regarded as a free surface of Cu diffusion and allow rapid surface diffusion of
Cu resulting in EM reliability concern. As indicated in Fig. 17.29, a flux divergence
555
F(t) = 1 − exp
−
t
η
β
(17.1)
where F(t) is percentage or fraction of the failed sample as a function of time, η is
the characteristic lifetime, and β is the shape factor or the slope of the Weibull plot.
In Black’s MTTF equation, there are three parameters: pre-factor A, current density
power factor n, and activation energy E a :
MTTF = A
j
−n
exp
E a
kT
(17.2)
With Black’s equation, we can determine those parameters experimentally and
obtain the statistical analysis. We need to conduct at the least the EM tests at two
temperatures and two current densities. To find the activation energy and to determine
n, we will not repeat them here, and the reader can use Google search or textbooks.
17.5.2 Experimental Studies of Electromigration in al
and Cu Interconnects
In the Al(Cu) interconnect, W via plugs are used to make vertical connections
between different layers of Al lines, for example, the M2 or M1 metallization layers
as shown in Fig. 17.29a. Since the atomic diffusion of W is much slower than Al,
there will be flux divergence of Al atoms as well as vacancies located over the top
of W via, and the divergence leads to hillock and void formation [37–40].
In comparison, the Cu dual-damascene structure is differently constructed [41,
42]. In Cu dual-damascene interconnects, the lower-level M2 trench and V1 that
connects to the M1 level are simultaneously prepared before Cu electroplating, as
shown in Fig. 17.29b. The M1 level is also separated from the V1 via by an electrically
conducting diffusion barrier (DB) that also coats the inner walls of V1 and the side
and bottom walls of the M2 trench. Consequently, the dual-damascene process places
the flux divergence, not at the V1/M2 interface, which is the top of V1 as in Al(Cu),
but at the M1/V1 interface at the bottom of V1. This via-bottom flux divergence is
potentially problematic from a reliability standpoint because only a small amount of
material depletion by EM will be sufficient for voiding damage to occur.
The dual-damascene interconnect is distinctly different from the previous Al(Cu)
architecture in another respect. It has been shown that EM in Cu interconnect occurs
by surface diffusion at the device operation temperature of 100 °C. In processing the
dual-damascene architecture, the top surface after electroplating must be chemicalmechanically polished and capped by a nitride layer before building of the next layer
[43]. Because of the weak chemical bonding between the nitride and Cu, the interface
can be regarded as a free surface of Cu diffusion and allow rapid surface diffusion of
Cu resulting in EM reliability concern. As indicated in Fig. 17.29, a flux divergence