550
Y. Wang et al.
under the same time of annealing, for microbump with Ni diffusion barrier, there is
still about 50% of microbump volume where the remaining solder was not converted
to IMC yet. We expect that such joint has better mechanical properties. Therefore, in
order to control Kirkndall void formation, besides adding Ni or Co into solder [11];
electroplating with nanotwin copper [13]; controlling electroplating bath chemistry
[14], the addition of Ni between Cu and solder as diffusion barrier seems to be a
promising approach. This is because the other three methods are more difficult in
finding a practical and cost effective route during operation and especially in control
of electroplating bath chemistry for mass production.
17.3.5 Concluding Remarks
Among the four types of microbump discussed above, symmetrical Cu/Ni/Sn/Ni/Cu
is one of the ideal and widely accepted metallurgical configurations of microbump
in the industry for 2.5D/3D IC technology. It has superior mechanical reliability
compared to other three metallurgical configurations: Cu/Sn/Cu; Ni/Sn/Ni and
Cu/Sn/Ni, in terms of Kirkendall void, porous void formation in Cu 3 Sn, IMC volume
contraction induced crack propagation, and asymmetrical impinging IMC interfacial
cracking.
17.4 Field Performance Prediction of 3D Packaging
As compared to traditional desktop and laptop, the mobile devices tend to adopt more
3-D technologies in order to reduce device size and weight. In the mean time, these
devices are exposed to more stringent and dynamic environments due to handheld.
However, the fundamentals to predict field performance is the same. One need to
understand. (1) Type of environmental/inherent stress that the devices experience and
duration across its usage life. (2) The failure modes that such stress can cause. (3)
Accelerated stress (run in lab) to duplicate such failure and (4) Acceleration model
to interpret lab tests results to field performance.
Taking microbump open failure as an example, the cause of the failure is typically
thermal cycling due to device power on/off and environmental temperature variation.
Cyclic stress-strain will deform the solder material due to CTE mismatch in different
electronic materials, thus inducing thermal fatigue failure. Thermal cycling (TC) or
thermal shock (TS) tests can be used for accelerated testing of 3D packaging. JEDEC
standard of temperature cycling provides different test conditions, where condition G
(−40~125 °C), J (0–100 °C), K (0–125 °C), L (−55~110 °C), and M (−40~150 °C)
as shown in Fig. 17.27 can be used with frequency of 1 cycle/hour and soak time of
15 min.
Y. Wang et al.
under the same time of annealing, for microbump with Ni diffusion barrier, there is
still about 50% of microbump volume where the remaining solder was not converted
to IMC yet. We expect that such joint has better mechanical properties. Therefore, in
order to control Kirkndall void formation, besides adding Ni or Co into solder [11];
electroplating with nanotwin copper [13]; controlling electroplating bath chemistry
[14], the addition of Ni between Cu and solder as diffusion barrier seems to be a
promising approach. This is because the other three methods are more difficult in
finding a practical and cost effective route during operation and especially in control
of electroplating bath chemistry for mass production.
17.3.5 Concluding Remarks
Among the four types of microbump discussed above, symmetrical Cu/Ni/Sn/Ni/Cu
is one of the ideal and widely accepted metallurgical configurations of microbump
in the industry for 2.5D/3D IC technology. It has superior mechanical reliability
compared to other three metallurgical configurations: Cu/Sn/Cu; Ni/Sn/Ni and
Cu/Sn/Ni, in terms of Kirkendall void, porous void formation in Cu 3 Sn, IMC volume
contraction induced crack propagation, and asymmetrical impinging IMC interfacial
cracking.
17.4 Field Performance Prediction of 3D Packaging
As compared to traditional desktop and laptop, the mobile devices tend to adopt more
3-D technologies in order to reduce device size and weight. In the mean time, these
devices are exposed to more stringent and dynamic environments due to handheld.
However, the fundamentals to predict field performance is the same. One need to
understand. (1) Type of environmental/inherent stress that the devices experience and
duration across its usage life. (2) The failure modes that such stress can cause. (3)
Accelerated stress (run in lab) to duplicate such failure and (4) Acceleration model
to interpret lab tests results to field performance.
Taking microbump open failure as an example, the cause of the failure is typically
thermal cycling due to device power on/off and environmental temperature variation.
Cyclic stress-strain will deform the solder material due to CTE mismatch in different
electronic materials, thus inducing thermal fatigue failure. Thermal cycling (TC) or
thermal shock (TS) tests can be used for accelerated testing of 3D packaging. JEDEC
standard of temperature cycling provides different test conditions, where condition G
(−40~125 °C), J (0–100 °C), K (0–125 °C), L (−55~110 °C), and M (−40~150 °C)
as shown in Fig. 17.27 can be used with frequency of 1 cycle/hour and soak time of
15 min.