2 3D Packaging Architectures and Assembly Process Design
31
constraints and a higher density of vias compared to the Via Middle and Via last
processes.
13 A key limitation of the Via First approach is that all the TSV materials and
processes need to be compatible with CMOS processes and temperatures (~1200 °C).
Polysilicon vias are mostly used in the Via First process [59]. Bauer et al. [57] discuss
a process where high density vias are created in a Via First process using a silicon
as a sacrificial material during the initial via formation step. The silicon is replaced
with W after the transistor formation processes are completed.
2. Via Middle (Also referred to as Mid-End of Line (MEOL) Via Process: In this
process TSV formation is after front-end device creation and before the creation
of all the back-end metal layers [60–66]. Key steps in this process are
(a) Front-end devices are fabricated including transistors and several lower
metal layers.
(b) Next, TSVs are created from the active device side typically at temperatures
in the 400–450 °C.
(c) The TSV is then plated with Cu or W.
(d) The wafer is then annealed at ~400 °C to relieve stresses in the TSV and to
stabilize the TSV metal structure.
(e) Next the wafer is planarized with a typical damascene process and is readied
for the remaining BEOL metallization.
(f) After BEOL metallization is complete, the wafer is mounted on a carrier
and thinned to reveal the TSV’s on the inactive (backside) of the wafer. Via
reveal is usually (optionally) followed by creation of a Re-Distribution Layer
(RDL) and backside bump formation processes that is a critical structure
for die stacking (see Fig. 2.12).
In addition to the use of Cu based vias, an advantage of the Via Middle process
is that subsequent chip fabrication processing temperatures are lower than for the
Via First process, and hence the thermal stresses induced in silicon due to the CTE
mismatch between the silicon and TSV metal are lower.
3. Via Last (Also referred to as Back-End of Line (BEOL) Via Process: In this
process, TSVs are created after the transistors and interconnects are created [67].
Key steps in this process are
(a) The transistors and the entire BEOL process is first completed.
(b) The wafer is then temporarily attached to a carrier using an adhesive (usually
referred to as a wafer bond/debond adhesive) on the active (front side).
(c) The wafer is thinned and the TSVs are formed using a similar process to
the Via Mid described earlier. This is followed by manufacturing of the
RDL and backside bumping. The backside RDL and bumping process are
essentially the same as described in Fig. 2.12.
13 While this statement seems intuitively feasible, the authors are not aware of an authoritative study
that establishes the design advantages of the Via First process over the Via Middle or Via Last
options.
31
constraints and a higher density of vias compared to the Via Middle and Via last
processes.
13 A key limitation of the Via First approach is that all the TSV materials and
processes need to be compatible with CMOS processes and temperatures (~1200 °C).
Polysilicon vias are mostly used in the Via First process [59]. Bauer et al. [57] discuss
a process where high density vias are created in a Via First process using a silicon
as a sacrificial material during the initial via formation step. The silicon is replaced
with W after the transistor formation processes are completed.
2. Via Middle (Also referred to as Mid-End of Line (MEOL) Via Process: In this
process TSV formation is after front-end device creation and before the creation
of all the back-end metal layers [60–66]. Key steps in this process are
(a) Front-end devices are fabricated including transistors and several lower
metal layers.
(b) Next, TSVs are created from the active device side typically at temperatures
in the 400–450 °C.
(c) The TSV is then plated with Cu or W.
(d) The wafer is then annealed at ~400 °C to relieve stresses in the TSV and to
stabilize the TSV metal structure.
(e) Next the wafer is planarized with a typical damascene process and is readied
for the remaining BEOL metallization.
(f) After BEOL metallization is complete, the wafer is mounted on a carrier
and thinned to reveal the TSV’s on the inactive (backside) of the wafer. Via
reveal is usually (optionally) followed by creation of a Re-Distribution Layer
(RDL) and backside bump formation processes that is a critical structure
for die stacking (see Fig. 2.12).
In addition to the use of Cu based vias, an advantage of the Via Middle process
is that subsequent chip fabrication processing temperatures are lower than for the
Via First process, and hence the thermal stresses induced in silicon due to the CTE
mismatch between the silicon and TSV metal are lower.
3. Via Last (Also referred to as Back-End of Line (BEOL) Via Process: In this
process, TSVs are created after the transistors and interconnects are created [67].
Key steps in this process are
(a) The transistors and the entire BEOL process is first completed.
(b) The wafer is then temporarily attached to a carrier using an adhesive (usually
referred to as a wafer bond/debond adhesive) on the active (front side).
(c) The wafer is thinned and the TSVs are formed using a similar process to
the Via Mid described earlier. This is followed by manufacturing of the
RDL and backside bumping. The backside RDL and bumping process are
essentially the same as described in Fig. 2.12.
13 While this statement seems intuitively feasible, the authors are not aware of an authoritative study
that establishes the design advantages of the Via First process over the Via Middle or Via Last
options.