32
R. Mahajan and B. Sankman
In the Via Last process, TSV processing temperatures are typically lower than
200 °C. This is important since the fully formed wafer is mounted on a carrier using
a low temperature adhesive. An advantage of this approach is that the thermal stress
issues are lower than with the Via First and Via Middle process options. However,
there are two significant concerns with the Via Last process. First since TSVs are
created after the BEOL, the TSVs need to land at the right metal layer in the chip
metal wiring. Special landing surfaces, also called catch cups, are included in silicon
metal layers to precisely locate the TSVs. Special care needs to be taken that the
TSVs land on catch cups and don’t accidentally punch through them. Integration of
catch cups requires careful design and restricts the placement of the TSVs. Secondly
since the TSVs are formed after complete wafer processing, yield loss due to TSV
formation could result in loss of valuable silicon.
Some of the key design attributes of TSVs are their diameter, pitch, aspect ratio
(i.e. the ratio of TSV diameter to its depth), electrical characteristics (including
resistivity of both the TSV and adjacent silicon, inductance, and frequency dependent
capacitance) and stress related KOZ’s. TSV aspect ratios are influenced by a few key
parameters such as the ability to get good insulation coverage as a function of via
depth and the ability to get void-free via filling. Table 2.1 shows some of the published
data on TSV diameters and depth. Electrical and stress characteristics are determined
by the TSV materials choices (including via metal, liner, adhesion materials, wafer
silicon doping) and process choices (deposition and anneal temperatures).
Table 2.1 Some recent TSV dimensions reported in the literature
References TSV diameter
(µm)
Silicon
thickness
(µm)
Aspect ratio
(Diameter:Depth)
TSV material Process
[40]
2
45
1:22.5
W
FEOL
[41]
5
150
1:30
Poly-silicon
FEOL
[42]
3
100
1:33.3
W
MEOL
[48]
10
50
1:5
Cu
BEOL
[43]
6
55
1:9
Cu
MEOL
[44]
10
50
1:5
Cu
MEOL
[49]
5
50
1:10
Cu
MEOL/BEOL
[50]
20
50
1:2.5
Cu
BEOL
[51]
2
30
1:15
Cu
Not specified
[46]
3
50
1:17
Cu
MEOL
R. Mahajan and B. Sankman
In the Via Last process, TSV processing temperatures are typically lower than
200 °C. This is important since the fully formed wafer is mounted on a carrier using
a low temperature adhesive. An advantage of this approach is that the thermal stress
issues are lower than with the Via First and Via Middle process options. However,
there are two significant concerns with the Via Last process. First since TSVs are
created after the BEOL, the TSVs need to land at the right metal layer in the chip
metal wiring. Special landing surfaces, also called catch cups, are included in silicon
metal layers to precisely locate the TSVs. Special care needs to be taken that the
TSVs land on catch cups and don’t accidentally punch through them. Integration of
catch cups requires careful design and restricts the placement of the TSVs. Secondly
since the TSVs are formed after complete wafer processing, yield loss due to TSV
formation could result in loss of valuable silicon.
Some of the key design attributes of TSVs are their diameter, pitch, aspect ratio
(i.e. the ratio of TSV diameter to its depth), electrical characteristics (including
resistivity of both the TSV and adjacent silicon, inductance, and frequency dependent
capacitance) and stress related KOZ’s. TSV aspect ratios are influenced by a few key
parameters such as the ability to get good insulation coverage as a function of via
depth and the ability to get void-free via filling. Table 2.1 shows some of the published
data on TSV diameters and depth. Electrical and stress characteristics are determined
by the TSV materials choices (including via metal, liner, adhesion materials, wafer
silicon doping) and process choices (deposition and anneal temperatures).
Table 2.1 Some recent TSV dimensions reported in the literature
References TSV diameter
(µm)
Silicon
thickness
(µm)
Aspect ratio
(Diameter:Depth)
TSV material Process
[40]
2
45
1:22.5
W
FEOL
[41]
5
150
1:30
Poly-silicon
FEOL
[42]
3
100
1:33.3
W
MEOL
[48]
10
50
1:5
Cu
BEOL
[43]
6
55
1:9
Cu
MEOL
[44]
10
50
1:5
Cu
MEOL
[49]
5
50
1:10
Cu
MEOL/BEOL
[50]
20
50
1:2.5
Cu
BEOL
[51]
2
30
1:15
Cu
Not specified
[46]
3
50
1:17
Cu
MEOL