16 Processing and Reliability of Solder Interconnections …
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16.1.2 3-D Packaging Variations
There are two primary 3-D packaging methodologies:—stacked die or stacked packages. As the terms imply, stacked die describes the mounting of individual die upon
one-another within a single, molded package. Interconnections began as wire bonds
between individual die. Through-silicon vias (TSVs) are now replacing wire bonds
in numerous products. Stacked packaging refers to the mounting of molded packages upon one-another. The earliest renditions of stacked packages used peripherally
leaded components [1]. This practice began by stacking gull-wing leaded packages
atop one-another to increase the memory die available on an assembly [2]. Today,
stacked packages are based upon the area-array interconnection format. Further integration is being achieved in stacked packaging technology by stacking dice with each
of the stacked packages.
Faced with market demands for miniaturization and increased product functionality, the consumer electronics industry has quickly moved from stacked packaging
to stacked die technology. However, stacked packaging remains more attractive to the
high-reliability electronics community. The particular advantage scenario is based
upon the known good die (KGD) concept, which is extended to the phrase, “known
good package.” Stacked packaging technology allows for verifying the performance
and reliability of each individual package through burn-in, qualification, and acceptance test regimens. Therefore, known good packages are established prior to their
assembly together and then to the PCB.
On the other hand, in the case of stacked die, wafer burn-in precedes die stacking
(mounting and wire bonding) and subsequent molding into the package. The packaged, stacked die component may be placed through a second series of burn-in,
qualification, and acceptance testing. However, with multiple die in each device,
there is an increased likelihood that die yield, when multiplied by three, four, or
however many dice are present, will reduce the yield of each stacked die package,
which also implies statistically, the potential for a reduced long-term reliability of the
stacked die component in the field. This chapter will focus on the stacked package
technology, which is the more promising approach for high-reliability electronics.
Although theoretically, many packages can be stacked upon one-another, there
are practical limitations. First, there are product design considerations. Consumer
products should be a thin as possible for portability. Secondly, an increased count
of individual packages requires additional signal routing to address added functional complexity, which results in the higher I/O counts that can increase the risk
of reduced assembly yields. Third, an increased number of packages in the stack
raises concern with thermal management, in particular, removing the heat generated
by a microprocessor die as well as from multiple memory dice. Fourth, manufacturability challenges add up with each package addition to the point they can interfere
with the clearances available in pick-and-place or reflow equipment. Lastly, taller
stacks increase their susceptibility to damage during handling and transportation
as well as reduced reliability caused by shock and vibration environments experienced in service. Therefore, the two common variants are: package-on-package (PoP)
473
16.1.2 3-D Packaging Variations
There are two primary 3-D packaging methodologies:—stacked die or stacked packages. As the terms imply, stacked die describes the mounting of individual die upon
one-another within a single, molded package. Interconnections began as wire bonds
between individual die. Through-silicon vias (TSVs) are now replacing wire bonds
in numerous products. Stacked packaging refers to the mounting of molded packages upon one-another. The earliest renditions of stacked packages used peripherally
leaded components [1]. This practice began by stacking gull-wing leaded packages
atop one-another to increase the memory die available on an assembly [2]. Today,
stacked packages are based upon the area-array interconnection format. Further integration is being achieved in stacked packaging technology by stacking dice with each
of the stacked packages.
Faced with market demands for miniaturization and increased product functionality, the consumer electronics industry has quickly moved from stacked packaging
to stacked die technology. However, stacked packaging remains more attractive to the
high-reliability electronics community. The particular advantage scenario is based
upon the known good die (KGD) concept, which is extended to the phrase, “known
good package.” Stacked packaging technology allows for verifying the performance
and reliability of each individual package through burn-in, qualification, and acceptance test regimens. Therefore, known good packages are established prior to their
assembly together and then to the PCB.
On the other hand, in the case of stacked die, wafer burn-in precedes die stacking
(mounting and wire bonding) and subsequent molding into the package. The packaged, stacked die component may be placed through a second series of burn-in,
qualification, and acceptance testing. However, with multiple die in each device,
there is an increased likelihood that die yield, when multiplied by three, four, or
however many dice are present, will reduce the yield of each stacked die package,
which also implies statistically, the potential for a reduced long-term reliability of the
stacked die component in the field. This chapter will focus on the stacked package
technology, which is the more promising approach for high-reliability electronics.
Although theoretically, many packages can be stacked upon one-another, there
are practical limitations. First, there are product design considerations. Consumer
products should be a thin as possible for portability. Secondly, an increased count
of individual packages requires additional signal routing to address added functional complexity, which results in the higher I/O counts that can increase the risk
of reduced assembly yields. Third, an increased number of packages in the stack
raises concern with thermal management, in particular, removing the heat generated
by a microprocessor die as well as from multiple memory dice. Fourth, manufacturability challenges add up with each package addition to the point they can interfere
with the clearances available in pick-and-place or reflow equipment. Lastly, taller
stacks increase their susceptibility to damage during handling and transportation
as well as reduced reliability caused by shock and vibration environments experienced in service. Therefore, the two common variants are: package-on-package (PoP)