2 3D Packaging Architectures and Assembly Process Design
27
4. 3 different system cooling
10 solutions are considered i.e.
(a) High thermal resistance cooling solutions which depend mainly on conduction (Typically encountered in laptop environments where active airflow is
not possible)
(b) Medium thermal resistance cooling solutions which use both conductive and
convective heat transfer (Typically encountered in desktop environments
that use cost-performance optimized cooling solutions)
(c) Low thermal resistance cooling solutions which use both conductive and
convective heat transfer (Typically encountered in server environments that
use performance optimized solutions to manage high TDP envelopes)
5. The Processor-DRAM and DRAM-DRAM interfaces, comprised of metallic
interconnects and protective underfill, are key interfaces that limit heat transport since the effective thermal conductivity (K) across that interface tends to be
in the approximate range (0.3–3.0 W/m °C), which is significantly lower than the
thermal conductivity of silicon (110 W/m °C) or Cu (390 W/m °C). Two different
interface conditions are considered for the analysis including a low interface with
K = 0.3 W/m °C and high interface with K = 3.0 W/m °C.
In cases where the system thermal resistance (i.e. the fully constructed final
product) is high relative to the package resistances, the impact of changes in package
resistance have a lesser influence on the overall TDP. In these cases, a system designer
can increase memory capacity and still take advantage of improved memory capacity
and power savings. As the performance of the system thermal cooling solution
improves, increasing package resistance (with increasing number of stacks) will
have a greater influence on the product’s TDP capability. In this scenario, the TDP
degradation and increasing the number of stacks is more significant. It can be seen
from Fig. 2.8 that since the bulk of the heat transfer in the package is conduction
based. For this case, improvements in the effective thermal conductivity of the interfaces between the stacked silicon chips are critical to improving the overall TDP
capability. The effective thermal conductivity of the interface can be improved by
increasing the number of micro-bumps between the die, and by increasing the effective thermal conductivity of the underfill, or polymeric encapsulants, used to increase
the reliability of the micro-bumps. Additionally there is a need to improve the quality
of system thermal solutions. Chapter 13 summarizes the various thermal solution
strategies developed to address the thermal management problem in 3D stacking.
In addition to Chap. 13, the chapter on thermal management in the Heterogeneous
Integration Roadmap (Chap. 20 in Ref. [7]) analyzes a series of canonical cases,
identifies limiting cases and describes thermal capability differences for different
architectures and points to potential solution paths.
It should also be noted that an assumption of uniform power distribution in
the processor is simplistic. In almost all cases a processor’s power distribution is
non-uniform. The presence of the additional thermal interfaces, and hence higher
10 System cooling refers to the cooling solution attached to the SIP.
27
4. 3 different system cooling
10 solutions are considered i.e.
(a) High thermal resistance cooling solutions which depend mainly on conduction (Typically encountered in laptop environments where active airflow is
not possible)
(b) Medium thermal resistance cooling solutions which use both conductive and
convective heat transfer (Typically encountered in desktop environments
that use cost-performance optimized cooling solutions)
(c) Low thermal resistance cooling solutions which use both conductive and
convective heat transfer (Typically encountered in server environments that
use performance optimized solutions to manage high TDP envelopes)
5. The Processor-DRAM and DRAM-DRAM interfaces, comprised of metallic
interconnects and protective underfill, are key interfaces that limit heat transport since the effective thermal conductivity (K) across that interface tends to be
in the approximate range (0.3–3.0 W/m °C), which is significantly lower than the
thermal conductivity of silicon (110 W/m °C) or Cu (390 W/m °C). Two different
interface conditions are considered for the analysis including a low interface with
K = 0.3 W/m °C and high interface with K = 3.0 W/m °C.
In cases where the system thermal resistance (i.e. the fully constructed final
product) is high relative to the package resistances, the impact of changes in package
resistance have a lesser influence on the overall TDP. In these cases, a system designer
can increase memory capacity and still take advantage of improved memory capacity
and power savings. As the performance of the system thermal cooling solution
improves, increasing package resistance (with increasing number of stacks) will
have a greater influence on the product’s TDP capability. In this scenario, the TDP
degradation and increasing the number of stacks is more significant. It can be seen
from Fig. 2.8 that since the bulk of the heat transfer in the package is conduction
based. For this case, improvements in the effective thermal conductivity of the interfaces between the stacked silicon chips are critical to improving the overall TDP
capability. The effective thermal conductivity of the interface can be improved by
increasing the number of micro-bumps between the die, and by increasing the effective thermal conductivity of the underfill, or polymeric encapsulants, used to increase
the reliability of the micro-bumps. Additionally there is a need to improve the quality
of system thermal solutions. Chapter 13 summarizes the various thermal solution
strategies developed to address the thermal management problem in 3D stacking.
In addition to Chap. 13, the chapter on thermal management in the Heterogeneous
Integration Roadmap (Chap. 20 in Ref. [7]) analyzes a series of canonical cases,
identifies limiting cases and describes thermal capability differences for different
architectures and points to potential solution paths.
It should also be noted that an assumption of uniform power distribution in
the processor is simplistic. In almost all cases a processor’s power distribution is
non-uniform. The presence of the additional thermal interfaces, and hence higher
10 System cooling refers to the cooling solution attached to the SIP.