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L. Chen et al.
stress integration, which is able to combine multiple field variables such as temperature, moisture concentration, vapor pressure, and void volume fraction. An example
of integrated stress analysis is then performed based on the theory. Section 15.5
summarizes the findings of thermo-mechanical and moisture induced stresses in 3D
packaging.
15.2 Thermal Stress and Its Effects on TSV Structures
15.2.1 Introduction
Due to the large thermal expansion mismatch between Cu TSVs and Si (α Cu =
17 ppm/
◦ C, α Si = 2.3 ppm/
◦ C), significant thermal stresses can be induced in and
around TSVs to cause serious reliability issues [28–31]. To successfully implement
TSVs in 3-D integration, it is essential to analyze and understand the characteristics
of thermal stresses at die level, as well as their impact on TSV structures.
The confinement by the surrounding Si results in complex stress state in and around
the TSV. The microstructure of Cu also plays an important role in controlling the
stress of the TSV structure. To capture these unique characteristics, this section will
first present stress analysis by both a semi-analytic method and numerical analysis,
followed by stress measurement using two complimentary techniques. Finally, two
reliability issues induced by stress, the device keep-out zone (KOZ) and via extrusion,
will be discussed.
15.2.2 Characteristics of TSV Stress by Semi-analytic
and Numerical Solutions
2-D plane-strain solution to the classical Lame problem has been employed to analyze
the thermal stresses of TSVs, but the 2D solution inherently could not capture the
3-D nature of the stress field near the wafer surface [32]. To overcome this limitation,
a semi-analytic solution is derived for an isolated TSV embedded in silicon using
a linear superposition method [33]. The stress contours calculated from the semianalytic solution are plotted in Fig. 15.1. At the wafer surface (z = 0), the normal stress
σ z is zero as required by the traction-free boundary condition and is non-uniform
away from the surface (Fig. 15.1a). At the wafer surface, the shear stress (σ rz ) has a
singular concentration at the via/Si interface (Fig. 15.1b), and the radial stress (σ r ) and
circumferential stress (σ θ ) are non-zero (Fig. 15.1c and Fig. 15.1d). Both the radial
and shear stresses contribute to the driving force for interfacial delamination. Because
the radial stress (σ r ) is tensile during cooling and compression during heating, the
driving force for interfacial delamination under cooling is about twice of that under
heating. Based on the semi-analytic solution, the steady-state energy release rate of
L. Chen et al.
stress integration, which is able to combine multiple field variables such as temperature, moisture concentration, vapor pressure, and void volume fraction. An example
of integrated stress analysis is then performed based on the theory. Section 15.5
summarizes the findings of thermo-mechanical and moisture induced stresses in 3D
packaging.
15.2 Thermal Stress and Its Effects on TSV Structures
15.2.1 Introduction
Due to the large thermal expansion mismatch between Cu TSVs and Si (α Cu =
17 ppm/
◦ C, α Si = 2.3 ppm/
◦ C), significant thermal stresses can be induced in and
around TSVs to cause serious reliability issues [28–31]. To successfully implement
TSVs in 3-D integration, it is essential to analyze and understand the characteristics
of thermal stresses at die level, as well as their impact on TSV structures.
The confinement by the surrounding Si results in complex stress state in and around
the TSV. The microstructure of Cu also plays an important role in controlling the
stress of the TSV structure. To capture these unique characteristics, this section will
first present stress analysis by both a semi-analytic method and numerical analysis,
followed by stress measurement using two complimentary techniques. Finally, two
reliability issues induced by stress, the device keep-out zone (KOZ) and via extrusion,
will be discussed.
15.2.2 Characteristics of TSV Stress by Semi-analytic
and Numerical Solutions
2-D plane-strain solution to the classical Lame problem has been employed to analyze
the thermal stresses of TSVs, but the 2D solution inherently could not capture the
3-D nature of the stress field near the wafer surface [32]. To overcome this limitation,
a semi-analytic solution is derived for an isolated TSV embedded in silicon using
a linear superposition method [33]. The stress contours calculated from the semianalytic solution are plotted in Fig. 15.1. At the wafer surface (z = 0), the normal stress
σ z is zero as required by the traction-free boundary condition and is non-uniform
away from the surface (Fig. 15.1a). At the wafer surface, the shear stress (σ rz ) has a
singular concentration at the via/Si interface (Fig. 15.1b), and the radial stress (σ r ) and
circumferential stress (σ θ ) are non-zero (Fig. 15.1c and Fig. 15.1d). Both the radial
and shear stresses contribute to the driving force for interfacial delamination. Because
the radial stress (σ r ) is tensile during cooling and compression during heating, the
driving force for interfacial delamination under cooling is about twice of that under
heating. Based on the semi-analytic solution, the steady-state energy release rate of