15 Die and Package Level Thermal and Thermal/Moisture Stresses …
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15.1 Introduction
3-D packaging with through-silicon vias (TSVs) is one of the key technologies implemented in semiconductor manufacturing in order to increase bandwidth, enhance
performance, shrink form factor, and reduce power [1–3]. Due to the introduction
of new features like TSV for providing short vertical interconnections, there exist
unique reliability requirements for 3D technology [4, 5]. Compared to conventional
2D packages, particular attention must be given to the new failure mechanisms of
TSV components and 3D chip stacks under various stress conditions [5–8].
Thermal stress in 3D package is generated due to the mismatch in coefficients of
thermal expansion (CTEs) between dissimilar materials when there is temperature
change. At die level, high thermal stress in TSV chips may cause many reliability
issues, including extrusion of TSV, cracking of silicon chip, and unintentional carrier
mobility change around TSVs. The issues in TSV chips will eventually affect the reliability of the whole 3D system. At package level, reliability issues caused by thermal
stresses may include fatigue fracture of solder ball joints and other interconnects, the
warping of dies, substrates and package, and the delamination and cracks initiated
at the interface between dissimilar materials [8–12]. The warping or non-uniformity
at package level can be especially critical because larger single die or multiple dies
are often used in 3D structure. The overall warpage of a chip-substrate structure will
affect the bonding process at board level [13].
In addition to thermal stress, particular attention is also given to moisture-induced
stress. A typical 3D package will contain moisture-sensitive materials, i.e., polymeric
materials at different levels, which can absorb a certain amount of moisture from the
ambient. Excessive moisture absorption may increase the corrosion rate of the metal
parts and aggravate the electro-chemical-migration [14, 15]. Moisture-induced stress,
such as hygroscopic stress, may also cause leakage to bulk chips, metal delamination,
cracking and extrusion in TVS chains [5], and the hygroscopic strain could be comparable or even higher than thermal strain [16–18]. More significantly, during reflow
soldering or the highly accelerated temperature and humidity stress test (HAST),
devastating material ruptures or interface delamination may take place. [19–27].
This chapter aims to provide fundamental theories, modeling and characterization
methods for analyzing the effects of thermal and moisture-induced stresses in 3D
packaging. First, the analysis and measurement of thermal stress in and around the
TSVs are presented in Sect. 15.2. The results reveal the near-surface characteristics
of thermal stress and the important role of Cu microstructure in controlling stress.
Stress-induced reliability issues, including the keep-out zone and via extrusion, are
discussed. In Sect. 15.3, thermal stress induced warpage at package level is studied.
Analytical modeling of an idealized multi-layered structure is described first. Then
several warpage control methods with experimental testing and numerical modeling
are introduced. A new warpage control method is presented to achieve warpage-free
flip-chip package. In Sect. 15.4, moisture-induced stress is calculated and coupled
with thermal stress to form an integrated stress modeling. A theoretical framework
based on damage micromechanics and effective stress concept is presented to achieve
433
15.1 Introduction
3-D packaging with through-silicon vias (TSVs) is one of the key technologies implemented in semiconductor manufacturing in order to increase bandwidth, enhance
performance, shrink form factor, and reduce power [1–3]. Due to the introduction
of new features like TSV for providing short vertical interconnections, there exist
unique reliability requirements for 3D technology [4, 5]. Compared to conventional
2D packages, particular attention must be given to the new failure mechanisms of
TSV components and 3D chip stacks under various stress conditions [5–8].
Thermal stress in 3D package is generated due to the mismatch in coefficients of
thermal expansion (CTEs) between dissimilar materials when there is temperature
change. At die level, high thermal stress in TSV chips may cause many reliability
issues, including extrusion of TSV, cracking of silicon chip, and unintentional carrier
mobility change around TSVs. The issues in TSV chips will eventually affect the reliability of the whole 3D system. At package level, reliability issues caused by thermal
stresses may include fatigue fracture of solder ball joints and other interconnects, the
warping of dies, substrates and package, and the delamination and cracks initiated
at the interface between dissimilar materials [8–12]. The warping or non-uniformity
at package level can be especially critical because larger single die or multiple dies
are often used in 3D structure. The overall warpage of a chip-substrate structure will
affect the bonding process at board level [13].
In addition to thermal stress, particular attention is also given to moisture-induced
stress. A typical 3D package will contain moisture-sensitive materials, i.e., polymeric
materials at different levels, which can absorb a certain amount of moisture from the
ambient. Excessive moisture absorption may increase the corrosion rate of the metal
parts and aggravate the electro-chemical-migration [14, 15]. Moisture-induced stress,
such as hygroscopic stress, may also cause leakage to bulk chips, metal delamination,
cracking and extrusion in TVS chains [5], and the hygroscopic strain could be comparable or even higher than thermal strain [16–18]. More significantly, during reflow
soldering or the highly accelerated temperature and humidity stress test (HAST),
devastating material ruptures or interface delamination may take place. [19–27].
This chapter aims to provide fundamental theories, modeling and characterization
methods for analyzing the effects of thermal and moisture-induced stresses in 3D
packaging. First, the analysis and measurement of thermal stress in and around the
TSVs are presented in Sect. 15.2. The results reveal the near-surface characteristics
of thermal stress and the important role of Cu microstructure in controlling stress.
Stress-induced reliability issues, including the keep-out zone and via extrusion, are
discussed. In Sect. 15.3, thermal stress induced warpage at package level is studied.
Analytical modeling of an idealized multi-layered structure is described first. Then
several warpage control methods with experimental testing and numerical modeling
are introduced. A new warpage control method is presented to achieve warpage-free
flip-chip package. In Sect. 15.4, moisture-induced stress is calculated and coupled
with thermal stress to form an integrated stress modeling. A theoretical framework
based on damage micromechanics and effective stress concept is presented to achieve