2 3D Packaging Architectures and Assembly Process Design
25
Fig. 2.6 (a) Schematic illustrating a side-by-side Processor-DRAM interconnect. (b) Schematic
illustrating a stacked Processor-DRAM interconnect
CPU accessed a WIO
5 memory through TSV’s). This is more than a 28× improvement.
6 This power efficiency, multiplied by the number of wires in the interface, and
combined with reduced data latency due to reduced interconnect lengths is what has
motivated designers to consider TSV based architectures. Another more relevant and
constrained comparison [45]
7 that restricts its scope to 2.5D
8 and 3D architectures
(Fig. 2.6a, b) shows that the 3D TSV case (Fig. 2.6b) has significantly reduced interconnect capacitance partly due to reduced interconnect length and partly due to a
different structure. As a result the 3D case has lower latency (15.7%) and requires
lower energy (32.2%) compared to the best known 2.5D case. The power efficiency
advantage is appealing across the application spectrum from handheld and mobile
devices where longer usage times between battery recharging can be enabled, to
servers where lower energy costs makes 3D TSV stacks attractive.
While energy efficiency and latency are the significant advantages for 3D TSV
based architectures a key limitation is that the maximum Thermal Design Power
(TDP) can be significantly lower than with comparable 2D configurations. This is
5 WIO i.e. Wide IO is a JEDEC standard memory where the memory die are connected by TSVs
[43].
6 Power efficiency quoted for the ESD case. See [44] for a detailed review of power and performance
differences between LPDDR and Wide-IO.
7 It is relevant to note that [45] also includes the case of monolithic 3-D ICs where multiple devices
levels are stacked within the wafer. This case is truly a bounding case of 3D integration but beyond
the scope of the current chapter. References [46, 47] covers this subject in more detail.
8 The 2.5D nomenclature is used here to maintain consistency with literature published before 2019
HIR [7].
25
Fig. 2.6 (a) Schematic illustrating a side-by-side Processor-DRAM interconnect. (b) Schematic
illustrating a stacked Processor-DRAM interconnect
CPU accessed a WIO
5 memory through TSV’s). This is more than a 28× improvement.
6 This power efficiency, multiplied by the number of wires in the interface, and
combined with reduced data latency due to reduced interconnect lengths is what has
motivated designers to consider TSV based architectures. Another more relevant and
constrained comparison [45]
7 that restricts its scope to 2.5D
8 and 3D architectures
(Fig. 2.6a, b) shows that the 3D TSV case (Fig. 2.6b) has significantly reduced interconnect capacitance partly due to reduced interconnect length and partly due to a
different structure. As a result the 3D case has lower latency (15.7%) and requires
lower energy (32.2%) compared to the best known 2.5D case. The power efficiency
advantage is appealing across the application spectrum from handheld and mobile
devices where longer usage times between battery recharging can be enabled, to
servers where lower energy costs makes 3D TSV stacks attractive.
While energy efficiency and latency are the significant advantages for 3D TSV
based architectures a key limitation is that the maximum Thermal Design Power
(TDP) can be significantly lower than with comparable 2D configurations. This is
5 WIO i.e. Wide IO is a JEDEC standard memory where the memory die are connected by TSVs
[43].
6 Power efficiency quoted for the ESD case. See [44] for a detailed review of power and performance
differences between LPDDR and Wide-IO.
7 It is relevant to note that [45] also includes the case of monolithic 3-D ICs where multiple devices
levels are stacked within the wafer. This case is truly a bounding case of 3D integration but beyond
the scope of the current chapter. References [46, 47] covers this subject in more detail.
8 The 2.5D nomenclature is used here to maintain consistency with literature published before 2019
HIR [7].