24
R. Mahajan and B. Sankman
2.2 3D TSV Based Architectures: Advantages
and Limitations
In the past few decades there has been considerable interest in 3D TSV based
SIP architectures [31–36], because of their compact construction and electrical
advantages. In 2019, there are three types of commercially widely available products with TSV’s. These are DRAM memory stacks, image sensors, and processors
[1, 2, 10, 37–40].
The electrical advantages include reduced signal latency, and lower signaling
power dissipation due to reduced interconnect lengths. Figure 2.5 shows the energy
consumption and dissipation during a 0 → 1 & a 1 → 0 bit transition based on
a simple capacitance model. Assuming the same Tx and Rx capacitance, energy
draw and dissipation is directly proportional to the capacitance of the interconnect
and this is where TSV’s have an advantage over traditional planar wire connections.
Since TSV’s are short length interconnects with significantly small capture pads than
standard substrates, they can exhibit a significantly lower (typically 4–20 times lower
[41]) interconnect capacitance compared to a side by side or planar interconnect. In
Fig. 2.6a, a memory is connected to the processor through a planar on-package
interconnect and in Fig. 2.6b the connection uses TSV’s.
A comprehensive calculation [42] shows that the interconnect power efficiency
(mW/Gbps) dropped from 15.65 mW/Gbps (for a bounding case where a DDR
memory in a DIMM slot was accessed by the CPU) to 0.55 mW/Gbps when the
Fig. 2.5 Simple capacitance model describing the energy consumption in a Tx (Transmitter)—Rx
(Receiver) interconnect link
R. Mahajan and B. Sankman
2.2 3D TSV Based Architectures: Advantages
and Limitations
In the past few decades there has been considerable interest in 3D TSV based
SIP architectures [31–36], because of their compact construction and electrical
advantages. In 2019, there are three types of commercially widely available products with TSV’s. These are DRAM memory stacks, image sensors, and processors
[1, 2, 10, 37–40].
The electrical advantages include reduced signal latency, and lower signaling
power dissipation due to reduced interconnect lengths. Figure 2.5 shows the energy
consumption and dissipation during a 0 → 1 & a 1 → 0 bit transition based on
a simple capacitance model. Assuming the same Tx and Rx capacitance, energy
draw and dissipation is directly proportional to the capacitance of the interconnect
and this is where TSV’s have an advantage over traditional planar wire connections.
Since TSV’s are short length interconnects with significantly small capture pads than
standard substrates, they can exhibit a significantly lower (typically 4–20 times lower
[41]) interconnect capacitance compared to a side by side or planar interconnect. In
Fig. 2.6a, a memory is connected to the processor through a planar on-package
interconnect and in Fig. 2.6b the connection uses TSV’s.
A comprehensive calculation [42] shows that the interconnect power efficiency
(mW/Gbps) dropped from 15.65 mW/Gbps (for a bounding case where a DDR
memory in a DIMM slot was accessed by the CPU) to 0.55 mW/Gbps when the
Fig. 2.5 Simple capacitance model describing the energy consumption in a Tx (Transmitter)—Rx
(Receiver) interconnect link