Chapter 14
Fundamentals of Advanced Materials
and Processes in Organic Substrate
Technology
Songhua Shi, Peter Tortorici, Sai Vadlamani, and Prithwish Chatterjee
14.1 Introduction
Over the past several decades, Moore’s law has successfully predicted integrated
circuit (IC) technology advancement. However, IC technology began hitting both
technology and cost barriers. Conventional die shrinkage and advanced deepsubmicron semiconductor technology is no longer able to meet the cost-toperformance ratio that the world desires in the near future. Three dimensional (3D)
packaging has caught broad attention and is poised to help continue the Moore’s law
by vertically integrating multiple IC chips into same footprint [1]. Although not all
substrates used in 3D packaging require higher wiring density or smaller feature size
than their non-3D counterparts, 3D packaging does accelerate the advancements in
substrate material and fabrication technology to enable overall smaller, faster, and
cheaper substrate demands. From a material innovation and fabrication technology
advancement perspective there are hardly any differences between 3D packaging and
2D/2.5D packaging technologies. Of the many challenges that are present in the path
of advancing substrates, substrate warpage control and building blocks for enabling
finer feature sizes are the ones that standout. In our understanding of the industry,
S. Shi (B) · P. Tortorici
Medtronic, 2343 W. Medtronic Way, Tempe, AZ 85281, USA
e-mail: shawn.shi@medtronic.com
P. Tortorici
e-mail: peter.c.tortorici@medtronic.com
S. Vadlamani (B) · P. Chatterjee
Intel Corporation, 5000 W Chandler Blvd, Chandler, AZ 85226, USA
e-mail: sai.vadlamani@intel.com
P. Chatterjee
e-mail: prithwish.chatterjee@intel.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_14
397
Fundamentals of Advanced Materials
and Processes in Organic Substrate
Technology
Songhua Shi, Peter Tortorici, Sai Vadlamani, and Prithwish Chatterjee
14.1 Introduction
Over the past several decades, Moore’s law has successfully predicted integrated
circuit (IC) technology advancement. However, IC technology began hitting both
technology and cost barriers. Conventional die shrinkage and advanced deepsubmicron semiconductor technology is no longer able to meet the cost-toperformance ratio that the world desires in the near future. Three dimensional (3D)
packaging has caught broad attention and is poised to help continue the Moore’s law
by vertically integrating multiple IC chips into same footprint [1]. Although not all
substrates used in 3D packaging require higher wiring density or smaller feature size
than their non-3D counterparts, 3D packaging does accelerate the advancements in
substrate material and fabrication technology to enable overall smaller, faster, and
cheaper substrate demands. From a material innovation and fabrication technology
advancement perspective there are hardly any differences between 3D packaging and
2D/2.5D packaging technologies. Of the many challenges that are present in the path
of advancing substrates, substrate warpage control and building blocks for enabling
finer feature sizes are the ones that standout. In our understanding of the industry,
S. Shi (B) · P. Tortorici
Medtronic, 2343 W. Medtronic Way, Tempe, AZ 85281, USA
e-mail: shawn.shi@medtronic.com
P. Tortorici
e-mail: peter.c.tortorici@medtronic.com
S. Vadlamani (B) · P. Chatterjee
Intel Corporation, 5000 W Chandler Blvd, Chandler, AZ 85226, USA
e-mail: sai.vadlamani@intel.com
P. Chatterjee
e-mail: prithwish.chatterjee@intel.com
© The Editor(s) (if applicable) and The Author(s), under exclusive
license to Springer Nature Singapore Pte Ltd. 2021
Y. Li and D. Goyal (eds.), 3D Microelectronic Packaging,
Springer Series in Advanced Microelectronics 64,
https://doi.org/10.1007/978-981-15-7090-2_14
397