394
S. G. Kandlikar and A. Ganguly
29. G. Brent, S.S. Sapatnekar, Placement of thermal vias in 3-D ICs using various thermal
objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4), 692–709 (2006)
30. D. Saha, S. Sur-Kolay, Guided GA-based multiobjective optimization of placement and assignment of TSVs in 3-D ICs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(8), 1742–1750
(August, 2019)
31. S. Das, J.R. Doppa, P.P. Pande, K. Chakrabarty, Monolithic 3D-enabled high performance and
energy efficient network-on-chip, in 2017 IEEE International Conference on Computer Design
(ICCD) (Boston, MA, 2017), pp. 233–240
32. S. Wang, K. Chakrabarty, M.B. Tahoori, Defect clustering-aware spare-TSV allocation in 3-D
ICs for YIELD enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10),
1928–1941 (2019)
33. Q. Xu, S. Chen, X. Xu, B. Yu, Clustered fault tolerance TSV planning for 3-D integrated circuits,
in I34EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
36, no. 8, pp. 1287–1300 (August, 2017)
34. B. Dang, M.S. Bakir, D.C. Sekar, C.R. King Jr., J.D. Meindl, Integrated microfluidic cooling
and interconnects for 2D and 3D chips. IEEE Trans. Adv. Packag. 33(1), 79–87 (2010)
35. HotSpot. http://lava.cs.virginia.edu/HotSpot/links.htm
36. D-ICE. http://esl.epfl.ch/3d-ice.html
37. P. Jacob, O. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft, J.F. McDonald, Predicting the
performance of a 3D processor-memory chip stack. Des. Test Comput. IEEE 22(6), 540–547
(2005)
38. L. Feihui, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, M. Kandemir, Design and
management of 3D chip multiprocessors using network-in-memory. ACM SIGARCH Comput.
Archit. News, IEEE Comput. Soc. 34(2), 130–141 (2006)
39. L. Benini, G. De Micheli, Networks on chips: a new SoC paradigm. Computer 35(1), 70–78
(2002)
40. M.S. Shamim, R.S. Narde, J.-L. Gonzalez-Hernandez, A. Ganguly, J. Venkatarman, S.G. Kandlikar, Evaluation of wireless network-on-chip architectures with microchannel-based cooling
in 3D multicore chips. Sustain. Comput.: Inf. Syst. 21, 165–178 (2019)
41. T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann, H. Reichl,
Interlayer cooling potential in vertically integrated packages. Miscrosyst. Technol. 15, 57–74
(2008). https://doi.org/10.1007/s00542-008-0690-4
42. Y. Zhang, A. Dembla, Y. Joshi M.S. Bakir, 3D stacked microfluidic cooling for highperformance 3D ICs, in 2012 IEEE 62nd Electronic Components and Technology Conference
(San Diego, CA, 2012), pp. 1644–1650. http://doi.org/10.1109/ECTC.2012.6249058
43. F. Alfieri, M.K. Tiwari, I. Zinovik, D. Poulikakos, T. Brunschwiler, B. Michel, 3D integrated
water cooling of a composite multilayer stack of chips, in Proceedings of the 14th International
Heat Transfer Conference, IHTC14, p. 9 (August 8–13, 2014)
44. G. Chen, J. Kuang, Z. Zeng, H. Zhang, E.F.Y. Young, B. Yu, Minimizing thermal gradient and
pumping power in 3D IC liquid cooling network design, in DAC’17: Proceedings of the 54th
Annual Design Automation Conference, vol. 70, pp. 1–6 (June, 2017). https://doi.org/10.1145/
3061639.3062285
45. B. Ding, Z.-H. Zhang, L. Gong, M.-H. Xu, Z.-Q. Huang, A novel thermal management scheme
for 3D-IC chips with multi-cores and high power density. Appl. Therm. Eng. 168, 114832
(2020). https://doi.org/10.1016/j.applthermaleng.2019.114832
46. C. Mandalapu, I. Abdel-Motaleb, S. Hong, R. Patti, Design, fabrication, and testing of a
liquid cooling platform for high power 3D-ICs, in 2019 8th International Symposium on Next
Generation Electronics (ISNE) (2019). http://doi.org/10.1109/ISNE.2019.8896611
47. C.A. Rubio-Jimenez, S. Kandlikar, A. Hernandez-Guerrero, Numerical analysis of novel micro
pin fin heat sink with variable fin density. IEEE Trans. Compon. Packag. Manuf. Technol. 2(5),
825–833 (May, 2012). https://doi.org/10.1109/tcpmt.2012.2189925
48. D. Lorenzini-Gutierrez, S.G. Kandlikar, Variable fin density flow channels for effective cooling
and mitigation of temperature nonuniformity in three-dimensional integrated circuits. J. Electr.
Packag. 136, 021007–0210011 (2014)
S. G. Kandlikar and A. Ganguly
29. G. Brent, S.S. Sapatnekar, Placement of thermal vias in 3-D ICs using various thermal
objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4), 692–709 (2006)
30. D. Saha, S. Sur-Kolay, Guided GA-based multiobjective optimization of placement and assignment of TSVs in 3-D ICs. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 27(8), 1742–1750
(August, 2019)
31. S. Das, J.R. Doppa, P.P. Pande, K. Chakrabarty, Monolithic 3D-enabled high performance and
energy efficient network-on-chip, in 2017 IEEE International Conference on Computer Design
(ICCD) (Boston, MA, 2017), pp. 233–240
32. S. Wang, K. Chakrabarty, M.B. Tahoori, Defect clustering-aware spare-TSV allocation in 3-D
ICs for YIELD enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10),
1928–1941 (2019)
33. Q. Xu, S. Chen, X. Xu, B. Yu, Clustered fault tolerance TSV planning for 3-D integrated circuits,
in I34EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
36, no. 8, pp. 1287–1300 (August, 2017)
34. B. Dang, M.S. Bakir, D.C. Sekar, C.R. King Jr., J.D. Meindl, Integrated microfluidic cooling
and interconnects for 2D and 3D chips. IEEE Trans. Adv. Packag. 33(1), 79–87 (2010)
35. HotSpot. http://lava.cs.virginia.edu/HotSpot/links.htm
36. D-ICE. http://esl.epfl.ch/3d-ice.html
37. P. Jacob, O. Erdogan, A. Zia, P.M. Belemjian, R.P. Kraft, J.F. McDonald, Predicting the
performance of a 3D processor-memory chip stack. Des. Test Comput. IEEE 22(6), 540–547
(2005)
38. L. Feihui, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, M. Kandemir, Design and
management of 3D chip multiprocessors using network-in-memory. ACM SIGARCH Comput.
Archit. News, IEEE Comput. Soc. 34(2), 130–141 (2006)
39. L. Benini, G. De Micheli, Networks on chips: a new SoC paradigm. Computer 35(1), 70–78
(2002)
40. M.S. Shamim, R.S. Narde, J.-L. Gonzalez-Hernandez, A. Ganguly, J. Venkatarman, S.G. Kandlikar, Evaluation of wireless network-on-chip architectures with microchannel-based cooling
in 3D multicore chips. Sustain. Comput.: Inf. Syst. 21, 165–178 (2019)
41. T. Brunschwiler, B. Michel, H. Rothuizen, U. Kloter, B. Wunderle, H. Oppermann, H. Reichl,
Interlayer cooling potential in vertically integrated packages. Miscrosyst. Technol. 15, 57–74
(2008). https://doi.org/10.1007/s00542-008-0690-4
42. Y. Zhang, A. Dembla, Y. Joshi M.S. Bakir, 3D stacked microfluidic cooling for highperformance 3D ICs, in 2012 IEEE 62nd Electronic Components and Technology Conference
(San Diego, CA, 2012), pp. 1644–1650. http://doi.org/10.1109/ECTC.2012.6249058
43. F. Alfieri, M.K. Tiwari, I. Zinovik, D. Poulikakos, T. Brunschwiler, B. Michel, 3D integrated
water cooling of a composite multilayer stack of chips, in Proceedings of the 14th International
Heat Transfer Conference, IHTC14, p. 9 (August 8–13, 2014)
44. G. Chen, J. Kuang, Z. Zeng, H. Zhang, E.F.Y. Young, B. Yu, Minimizing thermal gradient and
pumping power in 3D IC liquid cooling network design, in DAC’17: Proceedings of the 54th
Annual Design Automation Conference, vol. 70, pp. 1–6 (June, 2017). https://doi.org/10.1145/
3061639.3062285
45. B. Ding, Z.-H. Zhang, L. Gong, M.-H. Xu, Z.-Q. Huang, A novel thermal management scheme
for 3D-IC chips with multi-cores and high power density. Appl. Therm. Eng. 168, 114832
(2020). https://doi.org/10.1016/j.applthermaleng.2019.114832
46. C. Mandalapu, I. Abdel-Motaleb, S. Hong, R. Patti, Design, fabrication, and testing of a
liquid cooling platform for high power 3D-ICs, in 2019 8th International Symposium on Next
Generation Electronics (ISNE) (2019). http://doi.org/10.1109/ISNE.2019.8896611
47. C.A. Rubio-Jimenez, S. Kandlikar, A. Hernandez-Guerrero, Numerical analysis of novel micro
pin fin heat sink with variable fin density. IEEE Trans. Compon. Packag. Manuf. Technol. 2(5),
825–833 (May, 2012). https://doi.org/10.1109/tcpmt.2012.2189925
48. D. Lorenzini-Gutierrez, S.G. Kandlikar, Variable fin density flow channels for effective cooling
and mitigation of temperature nonuniformity in three-dimensional integrated circuits. J. Electr.
Packag. 136, 021007–0210011 (2014)