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S. G. Kandlikar and A. Ganguly
in a significant increase in the TSV length negatively affecting the performance of
the 3D interconnections which was the primary goal of using 3D IC technology.
Hence, careful co-design of interlayer cooling infrastructure, keeping the performance constraints of the target 3D IC, is necessary to achieve best thermal characteristics without compromising performance. Pivoting to 2.5D integration with an
interposer instead of 3D only partially solves the performance issue as it results in
longer planar wire lengths to interconnect the chips in the system, reducing overall
system performance and increasing power consumption [57]. Moreover, many interposer metal routing resources remain underutilized making the design sub-optimal
[58]. Limited pin counts on chip interfaces do not allow the extensive metal routing
resources to be fully utilized despite conscious design efforts. Therefore, while 2.5D
technology is a short-term solution to the challenges of 3D integration, eventually
they will not be able to provide the performance desired from high-performance
processors.
The design of microfluidic channels for cooling 3D ICs has received a lot of
attention in the recent years. Besides simply analyzing the cooling performance
as a function of channel dimensions and coolant characteristics, researchers have
introduced sophisticated and advanced features like fins, variable fin densities and
localized cooling to help alleviate high heat flux dissipation and thermal hotspot
issues in 3D ICs. We envision that in the near future non-TSV type 3D interconnection
technology using wireless, inductive or capacitive coupling methods can help us
overcome the electrical and thermal challenges in the 3D IC technology.
Acknowledgements The editors would like to thank Sangil Lee from Invensas Corporation,
Songhua Shi from Medtronic, and Ravi Mahajan from Intel Corporation for their critical review of
this Chapter.
References
1. S.G. Kandlikar, Review and projections of integrated cooling systems for 3D ICs. J. Electr.
Packag. 136(2), 024001, 11. http://doi.org/10:1115/1.4027175
2. D.B. Tuckerman, R.F. Pease, High performance heat sinking for VLSI. IEEE Electron Dev.
Lett. 2(5), 126–129 (1981)
3. S.G. Kandlikar, A.V. Bapat, Evaluation of Jet impingement, spray, and microchannel chip
cooling options for high heat flux removal. Heat Transfer Eng. 28(11), 911–923 (2007)
4. A.C. Cotler, E.R. Brown, V. Dhir, M.C. Shaw, Chip-Level spray cooling of an LD-MOSFET
RF Power amplifier. IEEE Trans. Comp. Packag. Technol. 27(2), 411–416 (2004)
5. C.J. Chang, H.T. Chen, C. Gau, Flow and heat transfer of a microjet impinging on a heated
chip: Part I—micro free and impinging jet. Nanoscale Microscale Thermophys. Eng. 17(1),
50–68 (2013)
6. M. Yue, S. Mahmoud, S. Quentin, C. Perceval, C. Jean-Phulippe, S. Abdelkader, F. Luc, G.
Christian, Study of miniaturizaption of a silicon vapor chamber for compact 3D microelectronics, via a hybrid analytical and finite element method. Trans. Netw. Commun. 7(6). https://
doi.org/10.14738/tnc.76.7569
S. G. Kandlikar and A. Ganguly
in a significant increase in the TSV length negatively affecting the performance of
the 3D interconnections which was the primary goal of using 3D IC technology.
Hence, careful co-design of interlayer cooling infrastructure, keeping the performance constraints of the target 3D IC, is necessary to achieve best thermal characteristics without compromising performance. Pivoting to 2.5D integration with an
interposer instead of 3D only partially solves the performance issue as it results in
longer planar wire lengths to interconnect the chips in the system, reducing overall
system performance and increasing power consumption [57]. Moreover, many interposer metal routing resources remain underutilized making the design sub-optimal
[58]. Limited pin counts on chip interfaces do not allow the extensive metal routing
resources to be fully utilized despite conscious design efforts. Therefore, while 2.5D
technology is a short-term solution to the challenges of 3D integration, eventually
they will not be able to provide the performance desired from high-performance
processors.
The design of microfluidic channels for cooling 3D ICs has received a lot of
attention in the recent years. Besides simply analyzing the cooling performance
as a function of channel dimensions and coolant characteristics, researchers have
introduced sophisticated and advanced features like fins, variable fin densities and
localized cooling to help alleviate high heat flux dissipation and thermal hotspot
issues in 3D ICs. We envision that in the near future non-TSV type 3D interconnection
technology using wireless, inductive or capacitive coupling methods can help us
overcome the electrical and thermal challenges in the 3D IC technology.
Acknowledgements The editors would like to thank Sangil Lee from Invensas Corporation,
Songhua Shi from Medtronic, and Ravi Mahajan from Intel Corporation for their critical review of
this Chapter.
References
1. S.G. Kandlikar, Review and projections of integrated cooling systems for 3D ICs. J. Electr.
Packag. 136(2), 024001, 11. http://doi.org/10:1115/1.4027175
2. D.B. Tuckerman, R.F. Pease, High performance heat sinking for VLSI. IEEE Electron Dev.
Lett. 2(5), 126–129 (1981)
3. S.G. Kandlikar, A.V. Bapat, Evaluation of Jet impingement, spray, and microchannel chip
cooling options for high heat flux removal. Heat Transfer Eng. 28(11), 911–923 (2007)
4. A.C. Cotler, E.R. Brown, V. Dhir, M.C. Shaw, Chip-Level spray cooling of an LD-MOSFET
RF Power amplifier. IEEE Trans. Comp. Packag. Technol. 27(2), 411–416 (2004)
5. C.J. Chang, H.T. Chen, C. Gau, Flow and heat transfer of a microjet impinging on a heated
chip: Part I—micro free and impinging jet. Nanoscale Microscale Thermophys. Eng. 17(1),
50–68 (2013)
6. M. Yue, S. Mahmoud, S. Quentin, C. Perceval, C. Jean-Phulippe, S. Abdelkader, F. Luc, G.
Christian, Study of miniaturizaption of a silicon vapor chamber for compact 3D microelectronics, via a hybrid analytical and finite element method. Trans. Netw. Commun. 7(6). https://
doi.org/10.14738/tnc.76.7569