390
S. G. Kandlikar and A. Ganguly
Fig. 13.12 Pressure drop Pressure drop variation along the flow length for interlayer configurations
shown in Fig. 13.4. Redrawn from [47]
their placement do not remain only a thermal issue. Nevertheless, this approach may
provide an additional pathway in the interlayer design.
Integration of TSVs and interlayer cooling requires codesign with electrical and
thermal engineers. Zhang et al. [50] discuss the design issues related to thermal
requirements as well as need to minimize TSV parasitics that impact latency, bandwidth density and power consumption. Alfieri et al. [44] studied the microchannel
interlayers with cylindrical pin fins using a porous medium approach considering the
conjugate conduction and convection heat transfer. This allowed them to analyze the
hot spots as well. They found that it is necessary to consider the property variations
and local thermal non-equilibrium as well as orthrotropic heat conduction.
13.7.2 Two-Phase Cooling
Two-phase cooling option is attractive because of the low flow rates as compared
to single-phase cooling, relative temperature uniformity, and ability to remove large
amounts of heat. For higher heat fluxes, the conventional microchannel designs with
two-phase flow are not satisfactory due to their instability issues, and lower performance [51]. However, recent developments have shown that it is possible to dissipate
heat fluxes greater than 1 kW/cm
2 using novel designs such as tapered microchanels
or microchannels with embedded pin fins operated at high flow rates [52–54]. The
header complexity with the tapered gap microchannels and high pressure drops with
micro pin-fins still remain outstanding issues. A recent review of two-phase cooling
for 3D IC by Green et al. [55] considers high heat flux dissipation as well as hot spot
cooling potential of several options, including localized microgaps over hot spots to
dissipate heat fluxes of 2 kW/cm
2 in the hot spot region. In spite of these research
efforts, a comprehensive demonstration of 3D IC stack that integrates electric and
S. G. Kandlikar and A. Ganguly
Fig. 13.12 Pressure drop Pressure drop variation along the flow length for interlayer configurations
shown in Fig. 13.4. Redrawn from [47]
their placement do not remain only a thermal issue. Nevertheless, this approach may
provide an additional pathway in the interlayer design.
Integration of TSVs and interlayer cooling requires codesign with electrical and
thermal engineers. Zhang et al. [50] discuss the design issues related to thermal
requirements as well as need to minimize TSV parasitics that impact latency, bandwidth density and power consumption. Alfieri et al. [44] studied the microchannel
interlayers with cylindrical pin fins using a porous medium approach considering the
conjugate conduction and convection heat transfer. This allowed them to analyze the
hot spots as well. They found that it is necessary to consider the property variations
and local thermal non-equilibrium as well as orthrotropic heat conduction.
13.7.2 Two-Phase Cooling
Two-phase cooling option is attractive because of the low flow rates as compared
to single-phase cooling, relative temperature uniformity, and ability to remove large
amounts of heat. For higher heat fluxes, the conventional microchannel designs with
two-phase flow are not satisfactory due to their instability issues, and lower performance [51]. However, recent developments have shown that it is possible to dissipate
heat fluxes greater than 1 kW/cm
2 using novel designs such as tapered microchanels
or microchannels with embedded pin fins operated at high flow rates [52–54]. The
header complexity with the tapered gap microchannels and high pressure drops with
micro pin-fins still remain outstanding issues. A recent review of two-phase cooling
for 3D IC by Green et al. [55] considers high heat flux dissipation as well as hot spot
cooling potential of several options, including localized microgaps over hot spots to
dissipate heat fluxes of 2 kW/cm
2 in the hot spot region. In spite of these research
efforts, a comprehensive demonstration of 3D IC stack that integrates electric and