13 Fundamentals of Heat Dissipation in 3D IC Packaging …
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dissipation of 150 W/cm
2 at a coolant volumetric flow rate of 0.8 L/min. Introducing
pin fins through which the TSVs were connected resulted in significantly higher
pressure drops. The authors provide extensive plots for 1–4 cm
2 chip areas depicting
thermal resistance and pressure drops performance with different microchannel and
pin fin configurations.
Zhang et al. [42] used an external air-cooled heat sink in conjunction with the
microfluidic interlayer channels. Alfieri et al. [44] studied the microchannel interlayers with cylindrical pin fins. Chen et al. [44] introduced configurable microchannel
passages that can be used to optimize the thermal gradients of the substrate and
pressure drops in the cooling liquid. They showed that under the test conditions,
the thermal gradients could be reduced by 84.0% and the pumping power could be
reduced by 37.65% as compared to straight channels. It clearly shows the advantages
of co-designing the thermal profile of the chip with the fluidic performance.
Ding et al. [45] numerically simulated the design of fin configurations in cooling
multicore regions of a chip. They employed clustered micro-pin fins on the core
regions and baffles on the surrounding region and obtained the maximum temperature in the core region and the toral pressure drop in the heat sink region of the
microchannel heat sink. The in-line & staggered micro-pin fins on the core regions
and single-layer baffles on the surrounding region were found to be the optimal
structure to balance the pumping power and heat transfer performance.
Mandalapu et al. [46] developed a test bench with embedded heaters and
microchannels with silicon pillars. They showed that incorporation of a diamond
layer reduced the hotspot temperature and was seen as critical in reducing the thermal
resistance in a 3D IC stack.
13.7.1 Thermal Performance Improvement with Variable Fin
Density in Microchannel Passages
The height of the TSV is an extremely important consideration in the cooling interlayer design. As shorter heights are employed to improve the TSV performance, the
flow resistance increases due to resulting smaller hydraulic diameters. Although the
heat transfer coefficient improves with the smaller diameters, the flow rate decreases
under a given pressure drop limit and the resultant heat dissipatio n decreases. This
makes it critical to utilize the available pressure drop in the most efficient manner.
Rubio-Jimenez et al. [47] proposed a variable fin density concept to accomplish this
goal as described below.
As the coolant traverses through the interlayer passages, its temperature rises
linearly assuming a constant heat flux and a uniform heat transfer coefficient (except
for the higher value at the entrance due to entrance effects). Figure 13.8 shows the
coolant and the substrate temperature profiles. The coolant as well as the substrate
reach their respective highest temperatures at the outlet section. However, the entire
387
dissipation of 150 W/cm
2 at a coolant volumetric flow rate of 0.8 L/min. Introducing
pin fins through which the TSVs were connected resulted in significantly higher
pressure drops. The authors provide extensive plots for 1–4 cm
2 chip areas depicting
thermal resistance and pressure drops performance with different microchannel and
pin fin configurations.
Zhang et al. [42] used an external air-cooled heat sink in conjunction with the
microfluidic interlayer channels. Alfieri et al. [44] studied the microchannel interlayers with cylindrical pin fins. Chen et al. [44] introduced configurable microchannel
passages that can be used to optimize the thermal gradients of the substrate and
pressure drops in the cooling liquid. They showed that under the test conditions,
the thermal gradients could be reduced by 84.0% and the pumping power could be
reduced by 37.65% as compared to straight channels. It clearly shows the advantages
of co-designing the thermal profile of the chip with the fluidic performance.
Ding et al. [45] numerically simulated the design of fin configurations in cooling
multicore regions of a chip. They employed clustered micro-pin fins on the core
regions and baffles on the surrounding region and obtained the maximum temperature in the core region and the toral pressure drop in the heat sink region of the
microchannel heat sink. The in-line & staggered micro-pin fins on the core regions
and single-layer baffles on the surrounding region were found to be the optimal
structure to balance the pumping power and heat transfer performance.
Mandalapu et al. [46] developed a test bench with embedded heaters and
microchannels with silicon pillars. They showed that incorporation of a diamond
layer reduced the hotspot temperature and was seen as critical in reducing the thermal
resistance in a 3D IC stack.
13.7.1 Thermal Performance Improvement with Variable Fin
Density in Microchannel Passages
The height of the TSV is an extremely important consideration in the cooling interlayer design. As shorter heights are employed to improve the TSV performance, the
flow resistance increases due to resulting smaller hydraulic diameters. Although the
heat transfer coefficient improves with the smaller diameters, the flow rate decreases
under a given pressure drop limit and the resultant heat dissipatio n decreases. This
makes it critical to utilize the available pressure drop in the most efficient manner.
Rubio-Jimenez et al. [47] proposed a variable fin density concept to accomplish this
goal as described below.
As the coolant traverses through the interlayer passages, its temperature rises
linearly assuming a constant heat flux and a uniform heat transfer coefficient (except
for the higher value at the entrance due to entrance effects). Figure 13.8 shows the
coolant and the substrate temperature profiles. The coolant as well as the substrate
reach their respective highest temperatures at the outlet section. However, the entire