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S. G. Kandlikar and A. Ganguly
dimension, can be accomplished in a single hop using the wireless links. In contrast,
in the 3D mesh architectures data transfer over even short vertical distances happen
over multi-hop paths over multiple switches resulting in higher energy dissipation
compared to the 3D-THiWiNoCs for both flit sizes. In addition, the interlayer cooling
chip reduces the temperature due to increased cooling capacity. Therefore, while the
bandwidth of the WiNoCs is less than that of the 3D mesh, the energy per bit and
peak temperatures are significantly reduced.
Based on the discussion above, one can infer that wireless 3D NoC coupled
with a cooling layer with microchannels is able to significantly improve the thermal
characteristics of the 3D IC compared to 3D mesh NoCs with TSVs and conventional
cooling while also reducing the energy cost per bit. This is due to reduction in multihop communication in both planar and vertical directions in a wireless 3D NoC.
However, due to removal of TSV based high bandwidth links across the cooling
layer, the bandwidth of this wireless NoC is lower than the 3D mesh. Hence, this
architecture is suitable in applications and environments that have strict constraints
on energy consumption and temperature of the system and do not require extremely
high bandwidths.
This method of reducing both energy and temperature of a 3D multicore IC is
orthogonal and can co-exist with other dynamic thermal and/or power management
mechanisms like DVFS which will provide further enhanced control and trade-offs
in the power-performance-temperature spectrum of the chip. Moreover, dynamic
control of the cooling capability of microchannels can be achieved by micro-pumps,
which can dynamically vary the flow rates in the channels. Such a mechanism together
with DVFS can be designed for a more holistic dynamic thermal control of a 3D
multicore chip in the future.
13.7 Liquid Cooling with Integrated Microchannels
Microchannels can be embedded as a cooling interlayer in a 3D IC chip stack. These
layers can be placed between each of the IC chips, or after each two or more chips.
The challenge faced by the microchannel cooling is its integration with the TSVs.
The TSVs can be located only at the channel walls, and hence large number of
closely spaced microchannels are desired. Combining this with the requirement of
short TSV distances, the desirable channel dimensions tend to be short and narrow
microchannels. Such channels will provide high heat transfer performance due to
small hydraulic diameters, but the coolant flow pressure drop through these channels
becomes prohibitively excessive.
Brunschweiler et al. [41] conducted an exhaustive study on the interlayer cooling
using water as the coolant in plain and pin fin populated microchannels of various
geometries. They showed that the application of this technique is severely challenged
due to the temperature rise as the channel hydraulic diameters are below 200 µm.
Effectively, high coolant flow rate is required resulting in excessive pressure drop. An
interlayer microchannel cooler with 200 µm hydraulic diameter resulted in a heat flux
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